Device and signal processing circuit for magnetic recording, magnetic recording apparatus
View Patent ↗A magnetic recording/reproducing apparatus includes a partial-response equalization circuit having frequency characteristic of cutting off low-frequency signal components inclusive of DC components; and a maximum-likelihood decoder, in which a reproduced signal outputted from the reproducing head is processed by the partial-response equalization circuit and then inputted into the maximum-likelihood decoder to be data-reproduced, thereby reducing a noise and distortion on the reproduced signal and reducing a data detection error rate.
1. A signal processing apparatus for a perpendicular magnetic recording/reproducing apparatus, comprising:
a partial-response equalization circuit including a digital filtering circuit having DC-null frequency characteristics cutting off low frequency signal components inclusive of DC components; and
a maximum likelihood decoder,
wherein a reproduced signal is reproduced by said partial-response equalization circuit and then inputted into said maximum-likelihood decoder to be reproduced Into a recording data sequence.
2. The signal processing apparatus according to claim 1 , comprising a magneto-resistive sensor to reproduce and output a signal of a perpendicular magnetic recording medium having a soft under layer.
3. The signal processing apparatus according to claim 1 , wherein a length n of an intersymbol interference is settable at longer than a five-bit interval for said partial-response equalization circuit end/or said maximum likelihood decoder.
4. The signal processing apparatus according to claim 1 , comprising a register circuit to set up an amplitude ratio of an intersymbol interference and/or a length n of the intersymbol-interference out.
5. The signal processing apparatus according to claim 1 , wherein reproduced signal waveforms corresponding to a pair of a closest two recording transitions recorded on a recording medium at a shortest bit-length interval are outputted as signal waveforms having intersymbol interference of an amplitude ratio of (a 1 , a 2 , a 3 , . . . ak, . . . , an) (in which k is an integer indicating a bit-interval, and a 1 . . . an are non-zero real numbers satisfying a relation: a 1 +a 2 +a 3 . . . ak+ . . . +an=0) at each bit-interval time through said partial-response equalization circuit, and wherein said reproduced signal waveforms are inputted into said maximum-likelihood decoder for data reproduction.
6. The signal processing apparatus according to claim 5 , wherein a 1 . . . an are non-zero real numbers satisfying the relation n≧3 at each bit-interval through said partial-response equalization circuit.
7. The signal processing apparatus according to claim 6 , wherein a 1 , a 2 and a 3 take an integer ratio of a 1 =4, a 2 =3 and a 3 =2.
8. The signal processing according to claim 7 , comprising a signal processing circuit wherein said signal processing circuit is mounted on a semiconductor integrated circuit.
9. The signal processing apparatus according to claim 8 , wherein said semiconductor integrated circuit is mounted on said perpendicular magnetic recording/reproducing apparatus.
10. The signal processing apparatus according to claim 6 , wherein said partial-response equalization circuit is constituted by a transversal filter in which filter tap coefficients are changed or adjusted so that a sum of said tap coefficients is zero.
11. The signal processing apparatus according to claim 10 , comprising a signal processing circuit wherein said signal processing circuit is mounted on a semiconductor integrated circuit.
12. The signal processing apparatus according to claim 11 , wherein said semiconductor integrated circuit is mounted on said perpendicular magnetic recording/reproducing apparatus.
13. The signal processing apparatus according to claim 1 , wherein reproduced signal waveforms corresponding to a pair of a closest two recording transitions recorded on a recording medium at a shortest bit-length interval are outputted as signal waveforms having intersymbol interference of an amplitude ratio of (a 1 , a 2 , a 3 −a 1 , . . . , ak−ak−2, . . . , an−an−2, −an−1, −an) (in which k is an integer indicating a bit-interval and a 1 . . . an are non-zero real numbers) at each bit-interval through said partial-response equalization circuit, and wherein said reproduced signal waveforms are inputted into said maximum-likelihood decoder for data reproduction.
14. The signal processing apparatus according to claim 1 , wherein said partial response equalization circuit has a DC-null frequency characteristic of not passing tow-frequency signal components inclusive of DC components.
15. A signal processing apparatus for a perpendicular magnetic recording/reproducing apparatus, comprising:
a partial-response equalization circuit having frequency characteristics cutting off low-frequency signal components inclusive of DC components; and
a maximum likelihood decoder,
wherein a reproduced signal is reproduced by said partial-response equalization circuit and then inputted into said maximum-likelihood decoder to be reproduced into a recording data sequence.
16. The signal processing apparatus according to claim 15 , comprising a magneto-resistive sensor to reproduce and output a signal of a perpendicular magnetic recording medium having a soft under layer.
17. The signal processing apparatus according to claim 15 , wherein reproduced signal waveforms corresponding to a pair of a closest two recording transitions recorded on a recording medium at a shortest bit-length interval are outputted as signal waveforms having intersymbol interference of an amplitude ratio of (a 1 , a 2 , a 3 , . . . , ak, . . . , an) (in which k is an integer indicating a bit-interval, and a 1 . . . an are non-zero real numbers satisfying the relation: a 1 +a 2 +a 3 . . . +ak+ . . . +an=0) at each bit-interval time through said partial-response equalization circuit, and said reproduced signal waveforms are inputted into said maximum-likelihood decoder for data reproduction.
18. The signal processing apparatus according to claim 17 , wherein a 1 . . . an are non-zero real numbers satisfying a relation n≧3 at each bit-interval through said partial-response equalization circuit.
19. The signal processing apparatus according to claim 18 , wherein a 1 , a 2 and a 3 take an integer ratio of a 1 =4, a 2 =3 and a 3 =2.
20. The signal processing apparatus according to claim 19 , comprising a signal processing circuit wherein said signal processing circuit is mounted on a semiconductor integrated circuit.
21. The signal processing apparatus according to claim 20 , wherein said semiconductor integrated circuit is mounted on said perpendicular magnetic recording/reproducing apparatus.
22. The signal processing apparatus according to claim 18 , wherein said partial-response equalization circuit is constituted by a transversal filter in which filter tap coefficients are changed or adjusted so that a sum of said tap coefficients is zero.
23. The signal processing apparatus according to claim 22 , comprising a signal processing circuit wherein said signal processing circuit is mounted on a semiconductor integrated circuit.
24. The signal processing apparatus according to claim 23 , wherein said semiconductor integrated circuit is mounted on said perpendicular magnetic recording/reproducing apparatus.
25. The signal processing apparatus according to claim 15 , wherein reproduced signal waveforms corresponding to a pair of a closest two recording transitions recorded on a recording medium at a shortest bit-length interval are outputted as signal waveforms having intersymbol interference of an amplitude ratio of (a 1 , a 2 , a 3 −a 1 , . . . , ak−ak−2, . . . an−an−2, −an−1, −an) (in which k is an integer indicating a bit-interval, and a 1 . . . an are non-zero real numbers) at each bit-interval through said partial-response equalization circuit, and said reproduced signal waveforms are inputted into said maximum-likelihood decoder for data reproduction.
26. The signal processing apparatus according to claim 15 , wherein said partial response equalization circuit has a DC-null frequency characteristic of not passing low-frequency signal components inclusive of DC components.