Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor

1. A method of fabricating an integrated silicon-germanium heterobipolar transistor wherein between a silicon-germanium base layer and a silicon emitter layer a silicon dioxide layer is formed, characterized in that said silicon dioxide layer is formed by means of Rapid Thermal Processing (RTP), wherein said base layer is heated in a sequence of temperature steps to a process temperature at which said silicon dioxide layer is subsequently formed and wherein in a first temperature step said base layer is heated to a temperature between 350° C. and 500° C.

2. The method as set forth in claim 1 wherein said silicon dioxide layer and said emitter layer are formed by means of a single continual process.

3. The method as set forth in claim 1 wherein said base layer is heated in a second temperature step to approximately 640° C.

4. The method as set forth in any of the claims 3 wherein said base layer 15 is heated in a third temperature step to approximately 705° C.

5. The method as set forth in claim 1 wherein said base layer is heated in a nitrogen atmosphere.

6. The method as set forth in claim 1 wherein said base layer 20 is exposed to an oxygen-nitrogen atmosphere for approximately 10 seconds.

7. The method as set forth in claim 1 wherein said silicon dioxide layer has a thickness between 0.3 nm and 0.4 nm, preferably approximately 0.35 nm.

8. The method as set forth in claim 1 wherein said silicon-germanium heterobipolar transistor is a pnp-bipolar transistor.

9. The method as set forth in claim 1 wherein an emitter layer is formed of polysilicon.

10. The method as set forth in claim 1 wherein the properties of said silicon dioxide layer are monitored during said RTP.

11. The method as set forth in claim 1 wherein the surface of said silicon-germanium base layer is pre-cleaned and said silicon dioxide layer is subsequently formed in a single continual process.

12. A method of fabricating an integrated circuit comprising the steps of:

forming a silicon-germanium base layer on a wafer;

transferring the silicon-germanium base layer to a Rapid Thermal Oxidation (RTO) chamber;

heating the silicon-germanium base layer using a sequence of temperature steps in the RTO chamber;

forming a silicon dioxide layer over the silicon-germanium base layer in said RTO chamber

transferring the silicon-germanium base layer from the RTO chamber after forming the silicon dioxide layer; and

forming a silicon emitter layer over the silicon dioxide layer.

13. The method of claim 12 , wherein said sequence of temperature steps comprises:

a first temperature step heating to a first temperature;

a second temperature step heating to a second temperature higher than said first temperature; and

a third temperature step heating to a third temperature higher than said second temperature.

14. The method of claim 13 , wherein said first temperature is in the range of 350° C. to 500° C.

15. The method of claim 13 , wherein said second temperature step comprises relatively quickly heating to the second temperature.

16. The method of claim 13 , wherein the second temperature is approximately 640° C.

17. The method of claim 13 , wherein said third temperature step comprises relatively slowly heating to the third temperature.

18. The method of claim 13 , wherein the third temperature is approximately 705° C.

19. The method of claim 12 , wherein said sequence of temperature steps comprises:

heating to a first temperature in the range of 350° C. to 500° C.;

relatively quickly heating to a second temperature higher than the first temperature; and

relatively slowly heating to a third temperature higher than said second temperature.