IP Library Granted Patent US 7,071,699
Granted Patent B2
US 7,071,699 · App. 10/825,448 · Granted Jul 4, 2006

Non-load driven fault monitor for electrical circuits

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,071,699
App. No.
10/825,448
Granted
Jul 4, 2006
Kind
B2
Abstract

A fault monitor for the load portion of an electrical circuit may be connected to an existing circuit by a single connection, and may detect flaws within the load portion of the circuit through the detection of changes in voltage through a resistor, caused by changes in current flow due to changing resistance within the load portion of the circuit.

Claims (14)

1. A method of testing for faults in an electrical circuit, the circuit having a load, the method comprising the steps of:

providing a fault monitor, having:

a power supply connected in series with a resistor;

a connection for connecting to the circuit with the load in parallel with the resistor;

a voltage sensor connectcd in series with the resistor; and

switching means for opening and closing the connection between the power supply and the resistor and load;

providing a test switching means connected in series with the resistor and in parallel with the current sensor, in sequence after the first transistor;

closing the test switching means;

determining whether voltage is sensed by the voltage sensor, thereby determining whether current is flowing through the load;

connecting the fault monitor to the circuit with the load in parallel with the resistor;

passing a current through the circuit and fault monitor; and

detecting the resulting voltage at the voltage sensor, thereby determining whether the total resistance provided by the load indicates a failure within the load and also determining a number of elements having faults within the load based on the difference between the resulting voltage and an expected voltage.

2. The method according to claim 1 , wherein the steps of closing the test switching means and determining whether voltage is sensed by the voltage sensor are performed before passing a current through the circuit and fault monitor, and detecting the resulting current at the current sensor.

3. The method according to claim 1 , wherein the steps of closing the test switching means and determining whether voltage is sensed by the voltage sensor are performed after passing a current through the circuit and fault monitor, and detecting the resulting voltage at the voltage sensor.

Assignments (3)
SECURITY INTEREST Recorded Jan 5, 2011
From: AEES INC.
To: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
Reel/Frame 026152/0083 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2009
From: ALCOA INC.
To: AEES INC.
Reel/Frame 022892/0750 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2004
From: WIELAND, STEPHEN; MAZORWICZ, EDWARD
To: ALCOA INC.
Reel/Frame 016019/0954 →