IP Library Granted Patent US 7,129,787
Granted Patent B1
US 7,129,787 · App. 10/826,460 · Granted Oct 31, 2006

Systems and methods for ramping power amplifier output power

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Quick Facts
Patent No.
US 7,129,787
App. No.
10/826,460
Granted
Oct 31, 2006
Kind
B1
Abstract

A power amplifier circuit including a first transistor, a second transistor, and a power control circuit. The first transistor includes a first input and a first output. The second transistor includes a second input coupled in series with the first output of the first transistor. The input circuit is coupled to the second input of the second transistor. The control circuit includes a time delay circuit and a variable source.

Claims (61)

1. A power amplifier circuit comprising:

a first transistor having a first input and an output

the first input being adapted to receive a high frequency signal in the Gigahertz range;

a second transistor having a second input coupled in series with the output of the first transistor

the second input being adapted to receive a low frequency signal in the Megahertz range,

wherein the low frequency input signal consumes no additional current;

an input circuit coupled to the first input of the first transistor; and

a power control circuit coupled to the second input of the second transistor, the power control circuit including:

a time delay circuit, and

a variable current source.

2. The circuit of claim 1 , wherein the time delay circuit includes at least one of a resistor and a capacitor.

3. The circuit of claim 2 , wherein at least one of the resistor and the capacitor are variable.

4. The power amplifier circuit of claim 1 , wherein the second input signal controls an envelope to the first input signal.

5. The envelope of claim 4 , wherein said envelope is used to form a curved ramp signal.

6. The power amplifier circuit of claim 1 , wherein the output of the second transistor comprises a signal that is proportional to the product of the output signal of the first transistor and the input signal to the second transistor.

7. A method of controlling power output of an amplifier comprising:

receiving a control signal;

producing a stepped power control signal having a plurality of power control steps, wherein producing each one of the plurality of steps includes:

producing a step voltage,

applying a time delay to the step voltage, and

applying the stepped power control signal to a power control input of the amplifier;

mixing said stepped power control signal with an exponential signal to smooth said power control signal and thereby eliminate undesirable harmonics at each step of said stepped power control signal;

generating an optimized linear transfer function curve for the amplifier by subdividing the time and amplitude into more than one steps wherein

each step is limited by at least two unequal time constants to avoid sharp transitions; and

adjusting the power output signal from a minimum level to a maximum desired level within a desired timeframe while substantially eliminating harmonics.

8. The method of claim 7 , wherein the control signal is a digital control signal.

9. The method of claim 7 , wherein the control signal determines a number of steps included in the plurality of steps.

10. The method of claim 7 , wherein at least one of the plurality of steps causes the amplifier to produce a desired output power level.

11. The stepped power control signal of claim 7 , comprising steps of equal magnitude.

12. The stepped power control signal of claim 7 , comprising steps of unequal magnitude.

13. The control signal of claim 7 , wherein the control signal is digital in nature.

14. The said steps of claim 7 , wherein each of the said steps are programmable according to a desired number of bits.

15. A method for minimizing undesirable harmonics in the power output of an amplifier comprising:

receiving a control signal;

producing a stepped power control signal including a plurality of power control steps, wherein producing each one of the plurality of steps includes:

producing a step voltage,

applying a time delay to the step voltage, and

applying the stepped power control signal to a power control input of the amplifier; and

eliminating a plurality of harmonics at each of the plurality of steps.

16. A method of controlling power output of an amplifier comprising:

receiving a control signal;

producing a stepped power control signal including a plurality of power control steps, wherein producing each one of the plurality of steps includes:

producing a step voltage,

applying a time delay to the step voltage, and

varying at least one aspect of the time delay to modify the time delay; and

applying the stepped power control signal to a power control input of the amplifier.

17. A method of controlling power output of an amplifier comprising:

receiving a control signal;

producing a stepped power control signal including a plurality of power control steps, wherein producing each one of the plurality of steps includes:

producing a step voltage, and

applying a time delay to the step voltage; and

applying the stepped power control signal to a power control input of the amplifier

wherein an elapsed time from a first one of the plurality of steps to a second one of the plurality of steps is less than a maximum ramp time, and

wherein the second one of the plurality of steps corresponds to a desired output power level of the amplifier.

18. A method of controlling power output of an amplifier comprising:

receiving a control signal;

producing a stepped power control signal including a plurality of power control steps, wherein producing each one of the plurality of steps includes:

producing a step voltage,

applying a time delay to the step voltage, and

eliminating a plurality of harmonics at each one of the plurality of steps; and

applying the stepped power control signal to a power control input of the amplifier.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE OF THE MERGER PREVIOUSLY RECORDED ON REEL 047642 FRAME 0417. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT, Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048521/0395 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047642/0417 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →