IP Library Granted Patent US 7,594,221
Granted Patent B2
US 7,594,221 · App. 10/827,523 · Granted Sep 22, 2009

Method and apparatus for translating binary code

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Quick Facts
Patent No.
US 7,594,221
App. No.
10/827,523
Granted
Sep 22, 2009
Kind
B2
Abstract

A method of translating binary code instructions from a source format to a target format for processing by a target processor includes converting a source instruction into a source intermediate data structure having a plurality of members, mapping the members in the source intermediate data structure to corresponding members in a target intermediate data structure according to a template, and converting the target intermediate data structure into a target instruction.

Claims (58)

1. A method of translating binary code instructions from a source format to a target format for processing by a target processor, said method comprising the steps of:

identifying a source instruction;

selecting a translation template corresponding to said identified source instruction, said template providing a set of target instructions semantically equivalent to said identified source instruction;

translating said identified source instruction in accordance with said template, wherein said translating comprises:

converting said identified source instruction into a source intermediate data structure having a plurality of members;

mapping said members in said source intermediate data structure to corresponding members in a target intermediate data structure according to said template; and

converting said target intermediate data structure into a target instruction; and

outputting said target instruction for processing by said target processor.

2. A method according to claim 1 in which said source and target instructions each include a control part and a data part and said control part of said source instruction being used in said identification step to identify said source instruction an instruction.

3. A method according to claim 2 wherein said data part from said source instruction is transformed into said corresponding data part or parts of said set of target instructions.

4. A method according to claim 3 in which said transformation step is carried out in accordance with a bit filling routine associated with said template.

5. A method according to claim 4 in which said bit filling routine is uniquely associated with said template.

6. A method according to claim 3 in which said transformation step is arranged to transform data of one type of endianness to data of another type of endianness.

7. A method according to claim 2 in which said source instruction control parts are each concatenated to provide a unique identifier and said templates are indexed in accordance with said identifiers.

8. A method according to claim 7 in which said templates are indexed by said unique identifiers in a look up table.

9. A method according to claim 1 in which said translation is carried out at runtime of an emulated application program.

10. A method according to claim 1 in which said templates are provided by software procedure calls.

11. A method according to claim 1 in which said source format is 32 bit and said target format is 64 bit.

12. A method according to claim 1 in which said source format is PA-RISC code and said target format is Itanium™ code.

13. An apparatus for translating binary code instructions from a source format to a target format for processing by a target processor, the apparatus comprising:

at least one processor configured to execute code embodied on a computer readable medium;

an instruction identifier embodied within said code for identifying a source instruction;

a template selector embodied within said code for selecting a translation template corresponding to said identified source instruction, said translation template comprising a set of target instructions semantically equivalent to said identified source instruction and further comprising input and output resources; and

a translator embodied within said code for translating said identified source instruction, wherein said translator is configured to

convert said identified source instruction into a source intermediate data structure having a plurality of members;

map said members in said source intermediate data structure to corresponding members in a target intermediate data structure according to said template; and

convert said target intermediate data structure into a target instruction; and

an output buffer embodied within said code for outputting said target instruction for processing by said target processor.

14. Apparatus according to claim 13 in which said source and target instructions each include a control part and a data part and said instruction identifier uses said control part of said source instruction to identify said source instruction.

15. Apparatus according to claim 14 in which said translator is operable to transform said data part from said source instruction into said corresponding data part or parts of said set of target instructions.

16. Apparatus according to claim 15 in which said transformation is carried out in accordance with a bit filling routine associated with said template.

17. Apparatus according to claim 16 in which said bit filling routine is uniquely associated with said template.

18. Apparatus according to claim 15 in which translator is operable to transform data of one type of endianness into data of another type of endianness.

19. Apparatus according to claim 14 in which said source instruction control parts are concatenated to provide a unique identifier and said templates are indexed in accordance with said identifiers.

20. Apparatus according to claim 19 in which said templates are indexed by said unique identifiers in a look up table.

21. Apparatus according to claim 13 in which said translation is carried out at runtime of an emulated application program.

22. Apparatus according to claim 13 in which said templates are provided by software procedure calls.

23. Apparatus according to claim 13 in which said source code has a 32 bit format and said target code has a 64 bit format.

24. Apparatus according to claim 13 in which said source code is PA-RISC code and said target code is Itanium™ code.

25. A computer program product for translating binary code instructions from a source format to a target format for processing by a target processor, comprising a computer-readable medium, further comprising:

a template embodied within said computer-readable medium for use in a binary code translator for translating binary code instructions from a source format to a target format for processing by a target processor, the template comprising:

a template identifier for uniquely associating said template to a source instruction;

a set of target instructions in a target format semantically equivalent to the source instruction;

computer usable program code embodied within said computer-readable medium configured to convert said source instruction into a source intermediate data structure having a plurality of members;

computer usable program code embodied within said computer-readable medium configured to map said members in said source intermediate data structure to corresponding members in a target intermediate data structure according to said template; and

computer usable program code embodied within said computer-readable medium configured to convert said target intermediate data structure into a target instruction.

26. A computer product according to claim 25 , further comprising a set of codes causing a computer to derive the template identifier from a control part of the source instruction.

27. A computer product according to claim 26 , wherein the template causes a computer to transform a data part of the source instruction into at least one corresponding data part of the set of target instructions.

28. A computer product according to claim 27 , further comprising a set of codes for causing a computer to bit fill the data part of the source instruction.

29. A computer product according to claim 26 , wherein the template causes a computer to create the template identifier by concatenating the control part of said source instruction.

30. A computer product according to claim 25 , wherein the template causing a computer to transform a source instruction having a 32 bit format to a target instruction having a 64 bit format.

31. A computer product according to claim 25 , wherein the template causes a computer to transform PA-RISC source code into Itanium™ target code.

32. A computer program product for translating binary code instructions from a source format to a target format for processing by a target processor, comprising:

a computer-readable medium, comprising:

a first set of codes for causing a computer to identify a source instruction;

a second set of codes for causing a computer to select a translation template corresponding to said identified source instruction, said template providing a set of target format instructions semantically equivalent to said identified source instruction;

a third set of codes for causing a computer to translate said identified source instruction in accordance with said template by converting said identified source instruction to an intermediate source data structure, mapping members of said intermediate source data structure to a members of a target intermediate data structure according to said template, and converting said target intermediate data structure into a target instruction; and

a fourth set of codes for causing a computer to output said translated instruction for processing by said target processor.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2021
From: OT PATENT ESCROW, LLC
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 056157/0492 →
PATENT ASSIGNMENT, SECURITY INTEREST, AND LIEN AGREEMENT Recorded Jan 26, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: OT PATENT ESCROW, LLC
Reel/Frame 055269/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2004
From: BHUSHAN, K N, KEERTHI; SANYAL, DIBYAPRAN; CHATTERJEE, ARIJIT
To: HEWLETT PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 015318/0882 →