High-speed distributed data processing system and method
View Patent ↗The invention is aimed at providing a high-speed processor system capable of performing distributed concurrent processing without requiring modification of conventional programming styles. The processor system in accordance with the invention has a CPU, a plurality of parallel DRAMs, and a plurality of cache memories arranged in a hierarchical configuration. Each of the cache memories is provided with an MPU which is binarily-compatible with the CPU and which has a function to serve as a processor.
1. An apparatus for controlling data processing in a first distributed memory with a control means, the apparatus comprising:
a memory; and
a central processing unit (CPU);
wherein said CPU is operable to cache out an area of said memory, to issue a control protocol to the control means of the first distributed memory, and to write data returned by the control means in response to the control protocol to the area that has been cached out in said memory.
2. The apparatus of claim 1 , further comprising the first distributed memory, wherein the distributed memory is arranged on a hierarchical level lower than that of the CPU.
3. The apparatus of claim 2 , wherein the control means is memory processing unit (MPU).
4. The apparatus of claim 2 , wherein the first distributed memory includes a plurality of memories, and wherein the plurality of memories are connected to said CPU in parallel.
5. The apparatus of claim 2 , wherein the first distributed memory is capable of accessing at least one second distributed memory, and said at least one second distributed memory is arranged on a hierarchical level lower than that of the first distributed memory.
6. The apparatus of claim 1 , wherein said CPU caches out said area of said memory and issues said control protocol to the control means of the first distributed memory by issuing a single extended instruction.
7. A method for distributed data processing by an apparatus including a central processing unit (CPU) and a memory, the method being carried out by said CPU and comprising the steps of:
caching out an area of said memory;
issuing a control protocol to a control means in a first distributed memory; and
writing data returned by the control means in response to the control protocol to the area that has been cached out in said memory.
8. The method of claim 7 , wherein the distributed memory is arranged on a hierarchical level lower than that of the CPU.
9. The method of claim 7 , wherein said CPU caches out said area of said memory and issues said control protocol to the control means of the first distributed memory by issuing a single extended instruction.
10. The method of claim 9 , wherein the control means is a memory processing unit (MPU), and wherein the single extended instruction is an intelligent prefetch instruction including said control protocol, said intelligent prefetch instruction causing the MPU both to execute a data processing program designated by said control protocol and to operate as a cache.