Memory with single and dual mode access
View Patent ↗The invention relates to a memory unit with at least two memory areas for storing data, first terminals for accessing data within the memory areas, and second terminals for accessing data within the memory areas. To provide multi-purpose access to the memory, the memory unit provides at least two access control means for providing selectively sole addressing and accessing data through one of the terminals, or individual addressing and accessing data through each of the terminals, respectively.
1. A memory unit comprising:
at least two memory areas configured to store data,
first terminals comprising a data port, the first terminals configured to access data within the memory areas,
second terminals comprising a data port, the second terminals configured to access data within the memory areas,
the first terminals and the second terminals comprising a control port and an address port, and
at least two access controllers selectively providing:
sole addressing and accessing data through one of the terminals, and
individual addressing and accessing data through each of the terminals, respectively,
wherein in case of sole addressing and accessing the data, the access controllers provide access to all of the at least two memory areas by a respective control port and address port of only one of the first terminals and second terminals and provide the data within all of the at least two memory areas through data ports of both the first terminals and second terminals.
2. The memory unit of claim 1 , wherein three memory areas are provided, and wherein a third memory area provides access by the control ports and the address ports of both of the terminals, respectively, and the data through the data ports of both of the terminals, respectively.
3. The memory unit of claim 2 , wherein two of the three memory areas provide access by the control ports and the address ports of the terminals, respectively, and the data through the data ports of the terminals, respectively.
4. The memory unit of claim 2 , wherein the access controllers provide prioritized access to the third memory area through one of the terminals.
5. The memory unit of claim 1 , wherein the address ports provide access to an external address bus.
6. The memory unit of claim 1 , wherein the first and/or second terminal data ports are configured to read and/or write data to and/or from the memory areas.
7. The memory unit of claim 1 , wherein the access controllers provide access to the data areas based on control and/or address signals at said terminals.
8. The memory unit of claim 1 , wherein the access controllers are state machines, the state machines providing access to the memory areas based on states of signals at the first and second terminals.
9. The memory unit of claim 1 , wherein the access controllers comprise memory registers.
10. The memory unit of claim 1 , wherein the access controllers provide access to at least one memory area by the control ports and the address ports of the terminals, respectively, and provide the data through the data ports of the terminals, respectively, in case of individual addressing.
11. The memory unit of claim 10 , wherein the access controllers provide access to at least one memory area by both of the control ports and the address ports of the terminals, and provide the data through the data ports of the terminals, respectively, in case of individual addressing.
12. The memory unit of claim 1 , wherein at least two memory areas are provided.
13. The memory unit of claim 1 , wherein programming the size of the memory areas is provided through one of the terminals.
14. The memory unit of claim 1 , wherein one of the terminals provides accessing the data by a central processing unit, and wherein one of the terminals provides accessing the data by a graphics processor.
15. The memory unit of claim 1 , wherein the bandwidth and/or clocking frequency for the terminals is different.
16. A module for providing memory to processors, comprising connection terminals providing communication between an electronic circuit and a memory unit according to claim 1 .
17. A mobile communication device comprising a memory unit according to claim 1 .
18. A method comprising:
receiving access signals and providing data from memory areas for storing data through first terminals comprising a data port,
receiving access signals and providing data from said memory areas through second terminals comprising a data port,
the first terminals and the second terminals comprising a control port and an address port, and
selectively receiving access signals solely through one of said first and second terminals and providing data from memory areas through both said first and second terminals, and
receiving access signals and providing data from memory areas through both of said first and second terminals individually, respectively,
wherein in case of sole addressing and accessing the data, the providing access to all of the memory areas is by a respective control port and address of only one of the first terminals and second terminals and the data within all of the memory areas is provided through data ports of both of said first terminals and second terminals.
19. The method of claim 18 , wherein three memory areas are provided, and wherein a third memory area is accessed by the control ports and the address ports of both of the terminals, respectively, and the data through the data ports of both of the terminals, respectively.
20. The method of claim 19 , wherein two of the three memory areas are accessed by the control ports and the address ports of the terminals, respectively, and the data through the data ports of the terminals, respectively.
21. The method of claim 19 , wherein the access controllers prioritizedly accesses the third memory area through one of the terminals.
22. The method of claim 18 , wherein control signals for controlling access to the memory areas are received by control ports of the first and/or second terminal.
23. The method of claim 18 , wherein addressing signals for addressing data within the memory areas are received by address ports of the first and/or second terminal.
24. The method of claim 23 , wherein an external address bus is accessed by the address ports provided.
25. The method of claim 18 , wherein data to and/or from the memory areas is read and/or written by data ports of the first and/or second terminal.
26. The method of claim 18 , wherein the access controllers access the data areas based on control and/or address signals at said first and second terminals.
27. The method of claim 18 , wherein the access controllers are state machines, the state machines accessing the data areas based on states of signals at the first and second terminals.
28. The method of claim 18 , wherein the access controllers accesses at least one memory area by the control ports and the address ports of the terminals, respectively, and provide the data through the data ports of the terminals, respectively, in case of individual addressing.
29. The method of claim 28 wherein the access controllers access at least one memory area by both of the control ports and the address ports of the terminals, and provide the data through the data ports of the terminals, respectively, in case of individual addressing.
30. A system for providing memory comprising:
a first processor, the first processor in communication with a memory unit through first terminals having a data port, and a second processor, the second processor in communication with the memory unit through second terminals having a data port,
the first terminals and the second terminals comprising a control port and an address port, and
at least two access controllers selectively providing:
sole addressing and accessing data by one of the processors, and
individually addressing and accessing data by each of the processors, respectively,
wherein in case of sole addressing and accessing the data, the access controllers provide access to all of the at least two memory areas by a respective control port and address port of only one of said first and second terminals and provide the data within all of the at least two memory areas through data ports of both of said first and second terminals.
31. A memory unit comprising:
at least first and second means for storing data,
first means for accessing data within the first and second means for storing data, said first means for accessing data, said first means for accessing data having a data port, and
second means for accessing data within the first and second means for storing data, said second means for accessing data having a data port,
the first means for accessing data and the second means for accessing data comprising a control port and an address port, and
means for selectively providing
sole addressing and accessing data through one of the first and second means for accessing data, and
individual addressing and accessing data through each of the first and second means for accessing data, respectively,
wherein in case of sole addressing and accessing the data, said means for selectively providing access to the first and second means for storing data is by a respective control port and address port of only one of the first and second means for accessing data within all of the at least two memory areas and provides the data within all of the at least two memory areas through data ports of both the first and second means for accessing data.
32. The memory unit of claim 31 , wherein three means for storing data are provided, and wherein the third means for storing data provides access by the control ports and the address ports of both of the first and second means for accessing data, respectively, and the data through the data ports of both of the first and second means for accessing data, respectively.
33. An apparatus, comprising:
at least two memory areas configured to store data,
first terminals having a data port configured to access data within the memory areas,
second terminals having a data port configured to access data within the memory areas,
the first terminals and the second terminals comprising a control port and an address port, and
at least two access controllers selectively providing:
sole addressing and accessing data through one of the terminals, and
individual addressing and accessing data through each of the terminals, respectively,
wherein in case of sole addressing and accessing the data, the access controllers provide access to both of the at least two memory areas by a respective control port and address port of only one of the first terminals and second terminals and provide the data within both of the at least two memory areas through data ports of both the first terminals and second terminals.