Component formation via plating technology
Improved terminations, interconnection techniques, and inductive element features for multilayer electronic components are formed in accordance with disclosed plating techniques. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such plated termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed varying width internal electrode tabs and additional anchor tab portions. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. The combination of electrode tabs and anchor tabs may be exposed in respective arrangements to form generally discoidal portions of plated material. Such plated material may ultimately form generally round portions of ball limiting metallurgy (BLM) to which solder balls may be reflowed. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and materials may be employed in the formation of the subject self-determining plated terminations and inductive components.
1. A method of making a multi-layer electronic component, comprising the steps of:
providing a plurality of dielectric layers;
providing a plurality of conductive tabs spirally aligned and interspersed among said plurality of dielectric layers, said plurality of conductive tabs respectively configured such that at least a portion thereof is exposed; and
plating a layer of termination material on the exposed portions of said conductive tabs whereby said plurality of tabs are connected together.
2. A method as in claim 1 , wherein the step of providing a plurality of conductive tabs comprises printing individual layers of conductive material at selected locations on selected surfaces of selected dielectric layers.
3. A method as in claim 1 , further comprising the step of:
exposing portions of the plurality of conductive tabs by opening a via through the plurality of dielectric layers prior to the step of plating.
4. A method as in claim 1 , wherein said step of plating comprises exposing said conductive tabs to an electroless copper solution.
5. A method of directing the formation of plating material in a multi-layer electronic component, comprising the steps of:
embedding a plurality of conductive tabs at selected locations in a plurality of layers of dielectric material, wherein said plurality of conductive tabs are respectively positioned at selected edges of said plurality of dielectric layers; and
exposing the plurality of conductive tabs to a plating solution whereby the embedded conductive tabs form nucleation points for plating material within the plating solution and guide the direction of the deposition of the plating material along the exposed plurality of conductive tabs wherein the exposed conductive tabs form a substantially planar discoidal formation.
6. The method of claim 5 , wherein the surface area and positioning of the exposed conductive tabs is varied whereby the surface area and geometry of the plating material is controlled.
7. The method of claim 5 , wherein the substantially discoidal formation of plating material is configured as ball limiting metallurgy.
8. The method of claim 6 , wherein the surface area and positioning of the exposed conductive tabs is varied such that the surface area of the plating material is formed into a substantially linear spiral formation.
9. The method of claim 8 , wherein the substantially linear spiral formation is configured as an inductive element.
10. A method of making a multi-layer electronic component, comprising the steps of:
providing a plurality of insulating substrates each having an upper and a lower surface, said substrates each being delimited laterally by edges;
interleaving a plurality of electrodes between selected of said plurality of insulating substrates;
exposing varied width portions of said electrodes along at least one edge of said plurality of substrates to form an exposed pattern of predetermined shape to facilitate formation of subsequent plating; and
plating at least one layer of termination material on the exposed portions of said electrodes.
11. The method of claim 10 , further comprising the step of continuing the plating process until the exposed portions of said electrodes are connected.
12. The method of claim 10 , wherein the step of plating is performed using an electroless process followed by an electrochemical process.
13. The method of claim 10 , wherein the step of plating is performed using an electroless process.
14. The method of claim 13 , wherein the electroless process comprises submersing the multi-layer electronic component in an electroless copper plating solution to form a copper termination layer.
15. The method of claim 14 , further comprising the step of covering the copper termination layer with a resistive layer.
16. The method of claim 15 , further comprising the step of plating the resistive layer with a conductive layer.
17. The method of claim 10 , wherein the step of exposing comprises:
providing the electrodes with non-uniformly cross-sectioned tab portions;
positioning the electrodes at laterally displaced locations among said dielectric layers; and
cleaving edges of the interleaved electrodes and dielectric layers whereby varied width portions of the tab portions of the electrodes are exposed.
18. The method of claim 17 , wherein said providing step comprises providing the electrodes with rounded tab portions.