Apparatus to reduce the internal frequency of an integrated circuit by detecting a drop in the voltage and frequency
View Patent ↗A semiconductor integrated circuit is disclosed that operates in synch with a clock signal supplied from an external source, and by a voltage supplied by a power supply. The circuit includes a detection means for detecting that at least one of a frequency of the clock signal and the supply voltage is reduced, and an internal voltage reduction means for lowering an internal voltage of the semiconductor integrated circuit when the detection means detects that at least one of the frequency and the supply voltage is lowered.
1. A memory semiconductor integrated circuit that operates in synch with a clock signal that is provided from outside, and based on a supply voltage provided by a power source, comprising:
a voltage drop detection unit configured to output a voltage drop detection signal in response to the supply voltage dropping below a predetermined voltage;
a clock frequency drop detection unit configured to output a frequency drop detection signal in response to a frequency of the clock signal dropping below a predetermined frequency; and
an internal voltage reduction unit configured to reduce an internal voltage of said semiconductor integrated circuit in response to at least one of the voltage drop detection signal and the clock frequency drop detection signal.
2. A memory circuit that operates in synch with a clock signal that is provided from outside and based on a supply voltage provided by a power source, comprising:
a voltage drop detection unit configured to output a voltage drop detection signal in response to the supply voltage dropping below a predetermined voltage; and
a clock frequency drop detection unit configured to output a frequency drop detection signal in response to a frequency of the clock signal dropping below a predetermined frequency; and
a timing adjustment unit configured to supply, to an internal circuit of the memory circuit, a timing adjustment signal for delaying timing of internal operations of the memory circuit in response to at least one of the voltage drop detection signal and the frequency drop detection signal.
3. A memory circuit that operates based on a supply voltage provided by a power source, comprising:
a voltage drop detection unit configured to output a voltage drop detection signal in response to the supply voltage dropping below a predetermined voltage;
a clock frequency drop detection trait configured to output a frequency drop detection signal in response to a frequency of the clock signal dropping below a predetermined frequency; and
a substrate voltage increasing unit configured to increase, in response to at least one of the frequency drop detection signal and the voltage drop detection signal, a voltage provided to a substrate on which said semiconductor integrated circuits is mounted by a predetermined amount.