Method of managing a multi-bit-cell flash memory
View Patent ↗A flash memory that supports N>1-bit programming is managed by, for at least one block of the memory, selecting the value of N to use for the block, designating one or more cells of the block as flag cells, and programming the flag cells to represent the selected value of N. Preferably, N is encoded according to whether the threshold voltages of the flag cells are greater or less than a reference voltage common to all values of N. The other cells of the block then are programmed in accordance with the selected value of N. N and its flag cells are selected when the block is first used to store data. Subsequent to an erasure of the block, a different value of N may be selected.
1. A method of managing a flash memory that includes at least one block, each block including a plurality of elements, each element having a respective threshold voltage, the method comprising:
for a first block of the at least one block:
selecting a first value of a parameter N of an N-bit programming mode associated with the first block;
designating a single cell of the first block to be a flag cell; and
setting the flag cell to represent the first value of the parameter N and programming at least one element of the first block other than the flag cell according to the N-bit programming mode,
wherein when the first value of the parameter N is greater than one, the flag cell is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag cell is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the first block.
2. The method of claim 1 , wherein setting the flag cell includes programming the flag cell, and wherein the programming of the flag cell is effected using a public write command.
3. The method of claim 1 , wherein setting the flag cell includes leaving the flag cell unprogrammed to represent the parameter N having the first value of one.
4. The method of claim 1 , further comprising determining the first value of the parameter N by reading the flag cell according to a 1-bit programming mode.
5. The method of claim 1 , wherein a particular element of the flash memory is programmed according to the N-bit programming mode by setting a threshold voltage of the particular element so that a reference voltage common to all values of the parameter N has a reference voltage value between the threshold voltage of the particular element and a threshold voltage of an unprogrammed element, and wherein the method further comprises determining the first value of the parameter N by comparing the threshold voltage of the flag cell to the reference voltage value.
6. The method of claim 5 , wherein the reference voltage value is greater than the threshold voltage of the unprogrammed element.
7. The method of claim 1 , further comprising:
selecting a second value of the parameter N; and
setting the flag cell to represent the second value of the parameter N.
8. The method of claim 7 , wherein, for the first block, the second value of the parameter N is identical to the first value of the parameter N.
9. The method of claim 7 , wherein the second value of the parameter N is different from the first value of the parameter N.
10. The method of claim 7 , further comprising erasing the first block subsequent to setting the flag cell to represent the first value of the parameter N and prior to setting the flag cell to represent the second value of the parameter N.
11. The method of claim 1 , wherein the first value of the parameter N is selected to be 2.
12. A memory device comprising:
a flash memory including a first block that includes a plurality of elements; and
a flash memory controller operative to:
select a value of a parameter N of an N-bit programming mode;
designate a single cell of the first block to be a flag cell; and
set the flag cell to represent the value of the parameter N and program at least one element of the first block other than the flag cell according to the N-bit programming mode,
wherein when the value of the parameter N is greater than one, the flag cell is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag cell is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the first block.
13. The memory device of claim 12 , wherein the flash memory is a NAND flash memory.
14. The memory device of claim 12 , wherein the flash memory controller is operative to select the value of the parameter N to be 2.
15. A system comprising:
a flash memory including a first block that includes a plurality of elements; and
a non-volatile memory to store program code associated with the first block, wherein the program code, when executed by a processor, causes the processor to:
select a value of a parameter N of an N-bit programming mode;
designate a single cell of the first block to be a flag cell; and
set the flag cell to represent the selected value of the parameter N and program an element of the first block other than the flag cell according to the N-bit programming mode,
wherein when the value of the parameter N is greater than one, the flag cell is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag cell is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the first block.
16. The system of claim 15 , wherein the flash memory is a NAND flash memory.
17. The system of claim 15 , wherein the value of the parameter N is selected to be 2.
18. A computer-readable storage medium storing computer-readable code to manage a flash memory that includes a first block, the first block including a plurality of elements, the computer-readable code comprising program code that, when executed by a processor, causes the processor to:
select a value of a parameter N of an N-bit programming mode;
designate a single cell of the first block as to be a flag cell; and
set the flag cell to represent the value of the parameter N and program an element of the first block other than the flag cell according to the N-bit programming mode,
wherein when the value of the parameter N is greater than one, the flag cell is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag cell is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the first block.
19. The computer-readable storage medium of claim 18 , wherein the value of the parameter N is selected to be 2.
20. A method of managing a plurality of non-volatile storage elements, each storage element having a corresponding storage window divisible into a plurality of ranges of storage levels representative of N bits of data, wherein N is an integer greater than zero, the method comprising:
selecting a first value of N for storing data in one of the non-volatile storage elements;
designating a single cell of the non-volatile storage elements to be a flag storage cell; and
setting the flag storage cell to represent the first value of N and programming at least one storage element of the non-volatile storage elements other than the flag storage cell according to an N-bit programming mode,
wherein when the value of N is greater than one, the flag storage cell is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag storage cell is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the non-volatile storage element.
21. The method of claim 20 , further comprising:
selecting a second value of N; and
setting the flag storage cell to represent the second value of N.
22. The method of claim 21 , further comprising erasing the non-volatile storage elements subsequent to setting the flag storage cell to represent the first value of N and prior to setting the flag storage cell to represent the second value of N.
23. A memory device comprising:
a plurality of non-volatile storage elements, each storage element having a corresponding storage window divisible into a plurality of ranges of storage levels representative of N bits of data, wherein N is an integer greater than zero; and
a controller to:
select a value of N for storing data in one of the non-volatile storage elements,
wherein a single cell of the non-volatile storage elements is designated to be a flag storage cell; and
set the flag storage cell to represent the value of N and program a storage element, other than the flag storage cell according to an N-bit programming mode,
wherein when the value of N is greater than one, the flag storage cell is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag storage cell is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the non-volatile storage element.
24. The memory device of claim 23 , wherein the storage elements are flash elements.
25. The memory device of claim 23 , wherein the storage elements are NAND flash elements.
26. A system comprising:
a plurality of non-volatile storage elements, wherein each storage element has a corresponding storage window divisible into a plurality of ranges of storage levels representative of N bits of data, wherein N is an integer greater than zero; and
a non-volatile memory storing program code to:
select a value of N for storing data in one of the non-volatile storage elements;
designate a single cell of the non-volatile storage elements to be a flag storage cell; and
set the flag storage cell to represent the value of N and program at least one storage element of the non-volatile storage elements other than the flag storage cell according to an N-bit programming mode,
wherein when the value of N is greater than one, the flag storage cell is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag storage cell is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the non-volatile storage element.
27. The system of claim 26 , wherein the storage elements are flash elements.
28. The system of claim 26 , wherein the storage elements are NAND flash elements.
29. A computer-readable storage medium storing computer-readable code to manage a plurality of non-volatile storage elements, wherein each storage element has a corresponding storage window divisible into a plurality of ranges of storage levels representative of N bits of data, wherein N is an integer greater than zero, the computer-readable code comprising processor executable instructions that, when executed by a processor, cause the processor to:
select a value of N for storing data in one of the non-volatile storage elements;
designate a single cell of the non-volatile storage elements to be a flag storage cell; and
set the flag storage cell to represent the selected value of N and program at least one storage element of the non-volatile storage elements other than the flag storage cell according to an N-bit programming mode,
wherein when the value of N is greater than one, the flag storage element is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag storage element is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the non-volatile storage element.
30. The method of claim 1 , wherein the flag storage cell is set by programming the flag storage cell according to the N-bit programming mode.
31. A method of managing a flash memory that includes at least one block, each block including a plurality of elements, each element having a respective threshold voltage, the method comprising:
for a first block of the at least one block:
selecting a first value of a parameter N of an N-bit programming mode associated with the first block;
setting a single flag cell of the first block to represent the first value of the parameter N;
programming an element of the first block, other than the flag cell, according to the N-bit programming mode; and
reading the flag cell and the element of the first block other than the flag cell,
wherein when the value of the parameter N is greater than one, the flag cell is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag cell is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the first block.
32. A memory device comprising:
a flash memory including a first block that includes a plurality of elements; and
a flash memory controller operative to:
select a value of a parameter N of an N-bit programming mode;
designate a single cell of the first block to be a flag cell;
set the flag cell to represent the value of the parameter N;
program an element of the first block, other than the flag cell, according to the N-bit programming mode; and
read the flag cell and the element of the first block other than the flag cell,
wherein a single-bit value “0” read from the flag cell corresponds to N=1 and wherein a dual-bit value “01” and a dual-bit value “10” of the flag cell correspond to multi-level operation of the first block.
33. A system comprising:
a flash memory including a first block that includes a plurality of elements; and
a non-volatile memory to store program code associated with the first block, wherein the program code, when executed by a processor, causes the processor to:
select a value of a parameter N of an N-bit programming mode;
designate a single cell of the first block to be a flag cell;
set the flag cell to represent the selected value of the parameter N;
program an element of the first block, other than the flag cell, according to the N-bit programming mode; and
read the flag cell and the element of the first block other than the flag cell,
wherein a single-bit value “0” read from the flag cell corresponds to N=1 and wherein a dual-bit value “01” and a dual-bit value “10” of the flag cell correspond to multi-level operation of the first block.
34. A computer-readable storage medium storing computer-readable code to manage a flash memory that includes a first block, the first block including a plurality of elements, the computer-readable code comprising program code that, when executed by a processor, causes the processor to:
select a value of a parameter N of an N-bit programming mode;
designate a single cell of the first block to be a flag cell;
set the flag cell to represent the value of the parameter N;
program an element of the first block, other than the flag cell, according to the N-bit programming mode; and
read the flag cell and the element of the first block other than the flag cell,
wherein when the value of the parameter N is greater than one, the flag cell is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag cell is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the first block.
35. A method of managing a plurality of non-volatile storage elements, each storage element having a corresponding storage window divisible into a plurality of ranges of storage levels representative of N≧1 bits of data, the method comprising:
selecting a first value of N to store data in one of the non-volatile storage elements;
designating a single cell of the non-volatile storage elements to be a flag storage cell;
setting the flag storage cell to represent the first value of N;
programming a storage element of the non-volatile storage elements other than the flag storage cell according to an N-bit programming mode; and
reading the flag storage cell and the storage element other than the flag storage cell,
wherein when the value of N is greater than one, the flag storage cell is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag storage cell is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the non-volatile storage element.
36. A memory device comprising:
a plurality of non-volatile storage elements, each storage element having a corresponding storage window divisible into a plurality of ranges of storage levels representative of N≧1 bits of data; and
a controller to:
select a first value of N to store data in one of the non-volatile storage elements;
designate a single cell of the non-volatile storage elements to be a flag storage cell;
set the flag storage cell to represent the first value of N;
program a storage element of the non-volatile storage elements, other than the flag storage cell, according to an N-bit programming mode; and
read the flag storage cell and the storage element other than the flag storage cell,
wherein when the value of N is greater than one, the flag storage cell is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag storage cell is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the non-volatile storage element.
37. A system comprising:
a plurality of non-volatile storage elements, each storage element having a corresponding storage window divisible into a plurality of ranges of storage levels representative of N≧1 bits of data; and
a non-volatile memory to store program code, wherein the program code, when executed by a processor, causes the processor to:
select a value of N to store data in one of the non-volatile storage elements, wherein a single cell of the non-volatile storage elements is designated to be a flag storage cell;
set the flag storage cell to represent the value of N;
program a storage element of the non-volatile storage elements, other than the flag storage cell according to an N-bit programming mode; and
read the flag storage cell and the storage element of the non-volatile storage elements other than the flag storage cell,
wherein when the value of N is greater than one, the flag storage cell is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag storage cell is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the non-volatile storage element.
38. A computer-readable storage medium storing computer-readable code to manage a plurality of non-volatile storage elements, wherein each storage element has a corresponding storage window divisible into a plurality of ranges of storage levels representative of N≧1 bits of data, the computer-readable code comprising processor executable instructions that, when executed by a processor, cause the processor to:
select a value of N to store data in one of the non-volatile storage elements;
designate a single cell of the non-volatile storage elements to be a flag storage cell;
set the flag storage cell to represent the value of N;
program a storage element of the non-volatile storage elements other than the flag storage cell according to an N-bit programming mode; and
read the flag storage cell and the storage element of the non-volatile storage elements other than the flag storage cell,
wherein when the value of N is greater than one, the flag storage cell is programmed according to the N-bit programming mode from an erased state such that only one bit of multiple bits stored at the flag storage cell is changed from an unprogrammed value to a programmed value to indicate multi-level operation of the non-volatile storage element.