Vertical thin film transistor
View Patent ↗A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate; forming a gate, having sidewalls and a thickness, overlying a substrate insulation layer; forming a gate oxide layer overlying the gate sidewalls, and a gate insulation layer overlying the gate top surface; etching the exposed substrate insulation layer; forming a first source/drain region overlying the gate insulation layer; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall with a channel length about equal to the thickness of the gate, interposed between the first and second source/drain regions.
1. A method for forming a vertical thin film transistor (V-TFT), the method comprising:
forming a gate, having sidewalls and a top surface, overlying a substrate insulation layer;
forming a gate insulation layer overlying the gate top surface;
forming a gate oxide layer overlying the gate sidewalls;
conformally depositing a silicon (Si) layer;
forming a first source/drain region overlying the gate insulation layer;
forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall;
forming a channel region overlying the first gate sidewall, interposed between the first and second source/drain regions; and,
wherein forming the first source/drain region, second source/drain region, and channel region includes forming the regions from the conformally deposited Si layer.
2. The method of claim 1 wherein forming a gate having sidewalls includes forming a gate with a first thickness; and,
wherein forming a channel region overlying the first gate sidewall includes forming a channel region with a channel length about equal to the first thickness.
3. The method of claim 2 wherein forming a gate with a first thickness includes the first thickness being in the range of 1000 to 6000 Å.
4. The method of claim 1 further comprising:
forming a lightly doped drain (LDD) in the channel region adjacent the first source/drain region.
5. The method of claim 1 further comprising:
providing a substrate made from a material selected from group including Si, quartz, glass, and plastic;
conformally depositing an insulating layer overlying the substrate, made from a material selected from the group including SiO2, SiO2/Si3N4/SiO2, and organic insulators such as polyimide; and,
following the formation of the gate, etching the exposed substrate insulation layer.
6. The method of claim 5 wherein forming a gate includes forming a gate on a substrate insulation layer having a surface along a first plane;
wherein etching the exposed substrate insulation layer includes forming a recess in the substrate insulation layer, lower than the first plane; and,
wherein forming a channel region overlying the first gate sidewall includes extending the channel region into the substrate insulation layer recess.
7. The method of claim 5 wherein forming a gate overlying the substrate insulation layer includes:
depositing a Si layer with the first thickness and sidewalls overlying the insulating layer; and,
doping the Si.
8. The method of claim 7 wherein forming a gate oxide layer overlying the gate sidewalls includes plasma oxidizing the gate Si layer sidewalls; and,
wherein forming a gate insulation layer overlying the gate top surface includes forming a gate insulation layer from a material selected from the group including SiO2 and Si3N4, having a thickness in the range of 25 to 500 Å.
9. The method of claim 5 wherein conformally depositing a Si layer overlying the gate insulation layer includes depositing an amorphous Si layer having a thickness in the range of 300 to 1000 Å;
the method further comprising:
performing a Vt adjust implant in the channel region; and,
crystallizing the amorphous Si layer.
10. The method of claim 9 wherein crystallizing the amorphous Si includes irradiating by excimer laser.
11. The method of claim 9 wherein crystallizing the amorphous Si layer includes:
depositing Ni overlying the amorphous Si layer; and, annealing.
12. The method of claim 9 further comprising:
depositing an absorption oxide layer overlying the amorphous Si layer, having a thickness in the range of 1000 Å to 1.5 microns; and
wherein crystallizing the amorphous Si layer includes excimer and CO2 laser irradiating the absorption oxide layer, to heat the underlying amorphous Si.
13. The method of claim 9 further comprising:
depositing a screen oxide layer overlying the amorphous Si layer, having a thickness in the range, of 300 to 1000 Å;
wherein forming first and second source/drain regions includes performing source/drain implants through the screen oxide layer; and,
the method further comprising:
performing an LDD implant through the screen oxide layer.
14. The method of claim 13 further comprising:
anisotropically etching the screen oxide layer to form a spacer.
15. The method of claim 1 further comprising:
depositing a silicide metal selected from the group including Ni, Ti, and Co, overlying the first and second source/drain regions;
annealing to form a metal silicide; and,
removing the unreacted metal.
16. The method of claim 5 further comprising:
conformally depositing an interlevel dielectric (ILD) overlying the transistor; and,
forming metal interconnects through the ILD to the first source/drain region, the second source/drain region, and the gate.
17. The method of claim 1 further comprising:
forming a third source/drain region overlying the substrate insulation layer, adjacent a second gate sidewall; and,
forming a channel region overlying the second gate sidewall, interposed between the first source/drain region and the third source/drain region adjacent the second gate sidewall.