Charge coupled device producing method
View Patent ↗A charge coupled device of the present invention includes a charge transfer region layer and a gate insulation film that are formed in the stated order on a semiconductor substrate, first gate electrodes formed at predetermined spaces on the gate insulation film, and second gate electrodes arranged between the first gate electrodes with at least silicon oxide films being interposed there between. Each silicon oxide film has constricted portions where the silicon oxide film is in contact with the gate insulation film, and electric insulation films are formed on the constricted portions so as to form sidewalls. This configuration decreases the charge transfer efficiency and increases a dielectric breakdown voltage between gate electrodes. Thus, a charge coupled device having high performance and high dielectric strength is provided.
1. A charge coupled device producing method comprising:
(a) forming a gate insulation film on a charge transfer region layer formed on a semiconductor substrate;
(b) forming a plurality of first gate electrodes on the gate insulation film so that the first gate electrodes are arranged at predetermined spaces;
(c) covering the first gate electrodes with silicon oxide films;
(d) forming at least an electric insulation film on the silicon oxide films and the gate insulation film;
(e) removing the electric insulation film so that the electric insulation film remains on constricted portions of the silicon oxide films in contact with the gate insulation film, thereby forming sidewalls; and
(f) forming second electrodes on the gate insulation film and the electric insulation films.
2. The charge-coupled device producing method according to claim 1 , wherein the removal of the electric insulation film in the step (e) is performed by anisotropic etching.
3. The charge coupled device producing method according to claim 1 , wherein, in (e), an etching rate with respect to the electric insulation film is higher than an etching rate with respect to the gate insulation film.
4. The charge coupled device producing method according to claim 2 , wherein, in (e), an etching rate with respect to the electric insulation film is 1 nm/minute to 10 nm/minute.
5. The charge coupled device producing method according to claim 1 , wherein the sidewalls have a substantially uniform thickness.
6. The charge coupled device producing method according to claim 1 , wherein each sidewall is brought into contact with the gate insulation film at a substantially right angle.
7. The charge coupled device producing method according to claim 1 , wherein the gate insulation film includes a silicon oxide film as its surface layer and the electric insulation film is a silicon nitride film.
8. The charge coupled device producing method according to claim 1 , wherein the gate insulation film includes a silicon nitride film as its surface layer and the electric insulation film is any one of a non-doped silicate glass (NSG) film, a tetraethoxysilane (TEOS) film, and a high temperature oxidation silicon oxide (HTO) film.
9. The charge coupled device producing method according to claim 1 , wherein each sidewall has a thickness in a range of 10 μm to 50 μm.
10. The charge coupled device producing method according to claim 1 , wherein the silicon oxide film has a thickness in a range of 10 μm to 50 μm.
11. The charge coupled device producing method according to claim 1 , wherein each space between the first gate electrodes is in a range of 50 μm and 100 μm.