Multiple simultaneous frequency and code acquisition for a code division multiple access (CDMA) communication system

1. A method for acquiring a signal in a wireless receiver, comprising:

receiving a signal in a receiver;

parallel processing the received signal in a plurality of matched filter stages, each matched filter stage comprising a plurality of registers, such that multiple codes are analyzed simultaneously, wherein the parallel processing further comprises:

applying a first stage matched filter by performing a bit-wise operation on a plurality of received signal samples;

applying a second stage matched filter by performing a bit-wise operation on a plurality of first stage frequency samples to develop a plurality of second stage signal samples;

applying a multi-point discrete Fourier transform (DFT) to the second stage signal samples, wherein the multi-point discrete Fourier transform (DFT) results in signals occupying a plurality of frequency bins and the method further comprises determining a power of each of the second stage signal samples;

averaging each of the signals within each of the multiple frequency bins to determine a maximum value; and

performing a timing drift compensation on the signals in the multiple frequency bins having a frequency offset.

2. The method of claim 1 , wherein the maximum value is used to determine frequency location.

3. The method of claim 1 , wherein the maximum value is used to determine a code offset location.

4. The method of claim 1 , wherein the timing drift compensation further comprises updating an average power value contained in a memory.

5. The method of claim 1 , further comprising performing the averaging step over a plurality of different tuning frequencies.

6. A multiple stage matched filter for a wireless receiver, comprising:

a receiver configured to develop a received signal, the received signal comprising a bit stream of signal samples;

a multiple stage matched filter comprising a plurality of matched filter stages, each matched filter stage comprising a plurality of registers, configured to parallel process the received signal such that multiple codes are analyzed simultaneously to determine a frequency offset;

a first stage matched filter configured to perform a bit-wise operation on a plurality of received signal samples;

a second stage matched filter configured to perform a bit-wise operation on a plurality of first stage frequency samples to develop a plurality of second stage signal samples;

logic for applying a multi-point discrete Fourier transform (DFT) to the second stage frequency samples;

wherein the multi-point discrete Fourier transform (DFT) results in signals occupying a plurality of frequency bins and the logic further comprises determining a power of each of the second stage signal samples;

logic for averaging each of the signals within each of the multiple frequency bins to determine a maximum value; and

a timing drift compensation element for performing a timing drift compensation on the signals having a frequency offset.

7. The multiple stage matched filter of claim 6 , wherein the maximum value is used to determine frequency location.

8. The multiple stage matched filter of claim 6 , wherein the maximum value is used to determine a code offset location.

9. The multiple stage matched filter of claim 6 , wherein the timing drift compensation further comprises updating an average power value contained in a memory.

10. The multiple stage matched filter of claim 6 , further comprising averaging over a plurality of different tuning frequencies.

11. A portable transceiver, comprising:

a modulator configured to receive and modulate a data signal;

an upconverter configured to receive the modulated data signal and provide a radio frequency (RF) signal;

a transmitter configured to transmit the RF signal;

a receiver configured to develop a received signal, the received signal comprising a bit stream of signal samples;

a multiple stage matched filter comprising a plurality of matched filter stages, each matched filter stage comprising a plurality of registers, configured to parallel process the received signal such that multiple codes are analyzed simultaneously to determine a frequency offset;

a first stage matched filter configured to perform a bit-wise operation on a plurality of received signal samples;

a second stage matched filter configured to perform a bit-wise operation on a plurality of first stage signal samples to develop a plurality of second stage signal samples;

logic for applying a multi-point discrete Fourier transform (DFT) to the second stage frequency samples, wherein the multi-point discrete Fourier transform (DFT) results in signals occupying a plurality of frequency bins and the logic comprises determining a power of each of the second stage signal samples;

logic for averaging each of the signals within each of the multiple frequency bins to determine a maximum value; and

logic for performing a timing drift compensation on the signals in the multiple frequency bins having a frequency offset.

12. The portable transceiver of claim 11 , wherein the maximum value is used to determine frequency location.

13. The portable transceiver of claim 11 , wherein the maximum value is used to determine a code offset location.

14. The portable transceiver of claim 11 , wherein the timing drift compensation further comprises updating an average power value contained in memory.

15. The portable transceiver of claim 11 , further comprising averaging over a plurality of different tuning frequencies.

16. A portable transceiver, comprising:

means for receiving a signal in a receiver;

means for parallel processing the received signal in a plurality of matched filter stages, each matched filter stage comprising a plurality of registers, such that multiple codes are analyzed simultaneously;

means for applying a first stage matched filter by performing a bit-wise operation on a plurality of received signal samples;

means for applying a second stage matched filter by performing a bit-wise operation on a plurality of first stage signal samples to develop a plurality of second stage signal samples;

means for applying a multi-point discrete Fourier transform (DFT) to the second stage frequency samples, wherein the multi-point discrete Fourier transform (OFT) results in signals occupying a plurality of frequency bins and the means for applying a multi-point discrete Fourier transform (OFT) to the second stage frequency samples further comprises determining a power of each of the second stage signal samples;

means for averaging each of the signals within each of the multiple frequency bins to determine a maximum value; and

means for performing a timing drift compensation on the signals in the multiple frequency bins having a frequency offset.

17. The portable transceiver of claim 16 , wherein the maximum value is used to determine frequency location.

18. The portable transceiver of claim 16 , wherein the maximum value is used to determine a code offset location.

19. The portable transceiver of claim 16 , wherein the timing drift compensation means further comprises means for updating an average power value contained in a memory.

20. The portable transceiver of claim 16 , further comprising means for averaging over a plurality of different tuning frequencies.