IP Library Granted Patent US 7,111,140
Granted Patent B2
US 7,111,140 · App. 10/832,421 · Granted Sep 19, 2006

Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices

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Quick Facts
Patent No.
US 7,111,140
App. No.
10/832,421
Granted
Sep 19, 2006
Kind
B2
Abstract

In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored. The storage system includes a memory controller coupled to the host; and a nonvolatile memory bank coupled to the memory controller via a memory bus, the memory bank being included in a non-volatile semiconductor memory unit, the memory bank has storage blocks each of which includes a first row-portion located in said memory unit, and a corresponding second row-portion located in each of the memory unit, each of the memory row-portions provides storage space for two of said sectors, wherein the speed of performing write operations is increased by writing sector information to the memory unit simultaneously.

Claims (8)

1. A memory storage system for increasing the performance of write operations of sector information to storage locations within non-volatile memory unit, the sector locations organized into sub-blocks and a plurality of sub-blocks defining a block comprising:

memory control circuitry, coupled to the non-volatile memory unit for receiving user data of sector information included in a sector, from a host, said received user data identifiable by addresses of a predetermined order, said memory control circuitry for writing said received user data to a first storage location of a particular sub-block of a particular block, said memory control circuitry for further writing user data of sector information to a first storage location of a sub-block of the particular block that is other than the particular sub-block regardless of the predetermined order of the addresses of the received sectors, a single virtual physical block address selectable based upon the identification of a free storage location within said non-volatile memory unit for identifying the storage locations of said sub-block of the particular block,

wherein writing of sector information to the first storage location of the sub-blocks of the particular block is performed substantially concurrently thereby increasing the performance of write operations.

2. A memory storage system as recited in claim 1 wherein said non-volatile memory unit includes one or more nonvolatile memory devices.

3. A memory storage system for increasing the performance of programming operations of sector information to storage locations within non-volatile memory unit, the sector locations organized into sub-blocks and a plurality of sub-blocks defining a block comprising:

memory control circuitry, coupled to the non-volatile memory unit, for receiving user data of sectors of information from the host, said received user data of sectors of information identifiable by addresses of a predetermined order, said memory control circuitry for programming sector information, received from the host, to a first storage location of a particular sub-block of a particular block, said memory control circuitry for further programming said user data of said sectors of information to a first storage location of a sub-block of the particular block that is other than the particular sub-block regardless of the predetermined order of the addresses of the received sectors, a single virtual physical block address selectable based upon the identification of a free storage location within said non-volatile memory unit for identifying the storage locations of said sub-block of the particular block,

wherein programming of sector information to the first storage location of the sub-blocks of the particular block is performed substantially concurrently thereby increasing the performance of programming operations.

4. A memory storage system as recited in claim 3 wherein said non-volatile memory unit includes one or more nonvolatile memory devices.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
MERGER Recorded Jun 11, 2013
From: LEXAR MEDIA, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 030588/0368 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2006
From: ESTAKHRI, PETRO; IMAN, BERHANU
To: LEXAR MEDIA, INC.
Reel/Frame 017287/0312 →