Image quality improvement for liquid crystal displays
View Patent ↗A liquid crystal display (LCD) system, comprising a matrix of pixels, analyzes a video data stream for grayscale level jumps from extreme black to moderate gray levels. Transitions in grayscale levels are restricted between adjacent pixels so as to reduce image degradation due to fringe field effects. A memory, such as a plurality of shift registers, may be used to store grayscale levels of adjacent pixels which are compared and if a ratio between these grayscale levels exceeds a desire value then at least one of the grayscale levels is modified.
1. An apparatus for improving image quality of a liquid crystal display (LCD) comprising a matrix of pixels arranged in a plurality of rows and columns, wherein an intersection of a row and a column defines a position of a pixel in the matrix, said apparatus comprising:
at least one digital-to-analog converter (DAC) having a digital input and an analog output;
a plurality of column switches adapted for coupling the analog output of said at least one DAC to each of a plurality of columns of a matrix of pixels of a liquid crystal display (LCD);
a plurality of row switches adapted for selectively coupling each of a plurality of rows to said plurality of columns;
column control logic for controlling said plurality of column switches;
row control logic for controlling said plurality of row switches;
a video frame to gray scale conversion and pixel address logic for converting video information into LCD gray scale values and corresponding pixel address locations thereof; and
video data comparator/modifier logic, said video data comparator/modifier logic adapted to receive the LCD gray scale values for each pixel of the matrix of pixels, wherein gray scale values of adjacent pixels are compared and if a ratio of the gray scale values of adjacent pixels is greater than a desired value, then one of the gray scale values is modified so that the ratio of adjacent pixel gray scale values is no greater than the desired value;
said video data comparator/modifier logic is adapted for sending all unmodified gray scale values and any modified gray scale values to said at least one DAC;
said video frame to gray scale conversion and pixel address logic adapted for sending said pixel address locations to said column control logic and said row control logic.
2. The apparatus of claim 1 , wherein the desired value is two.
3. The apparatus of claim 1 , further comprising a video memory for storing said LCD gray scale values.
4. The apparatus of claim 1 , further comprising a video memory for storing said unmodified and said modified LCD gray scale values.
5. The apparatus of claim 1 , further comprising a video memory coupled to said video data comparator/modifier logic.
6. The apparatus of claim 1 , wherein said video data comparator/modifier logic comprises a plurality of registers adapted for storing gray scale values for at least N adjacent pixels.
7. The apparatus of claim 6 , wherein said video data comparator/modifier logic comprises a level writing decision logic for determining the ratio of the adjacent pixel LCD gray scale values.
8. The apparatus of claim 7 , wherein said level writing decision logic determines which of said LCD gray scale values are to be modified.
9. The apparatus of claim 6 , wherein N is equal to eight.
10. The apparatus of claim 6 , wherein N is equal to six.
11. The apparatus of claim 6 , wherein N is equal to ten.
12. The apparatus of claim 6 , wherein N is selected from the group consisting of 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 and 16.
13. The apparatus of claim 1 , further comprising a gray scale look-up table coupled between said video data comparator/modifier logic and said at least one DAC.
14. The apparatus of claim 1 , wherein said LCD, said plurality of column switches and said plurality of row switches are fabricated on a semiconductor integrated circuit.
15. The apparatus of claim 1 , wherein said LCD, said plurality of column switches, said plurality of row switches, said column control logic, and said row control logic are fabricated on a semiconductor integrated circuit.
16. The apparatus of claim 1 , wherein said video frame to gray scale conversion and pixel address logic, said video data comparator/modifier logic and said at least one DAC are fabricated on at least one semiconductor integrated circuit.