Hardware structure for a transmission/reception device for mobile radio applications, and method for processing data in such a transmission/reception device

1. A transmission/reception device for mobile radio applications for a third or higher generation mobile station, comprising:

a microprocessor,

a plurality of task-specific processors, wherein each task-specific processor can be configured such that a basic function performed by the task-specific processor can be controlled by changing configuration parameters, where, following configuration, the task-specific processor performs data processing in line with a function determined by the configuration,

a bidirectional processor interface which connects the microprocessor and the plurality of task-specific processors to one another via a first bus,

wherein the first bus connects the processor interface associated with the microprocessor with the task-specific processors, and

a second bus, which connects the microprocessor and at least one of the task-specific processors to one another for the purpose of data interchange, wherein

the microprocessor has an associated configuration table and the entries in the configuration table comprise control data which are calculated beforehand in a task-specific processor and are transferred to the microprocessor via the processor interface,

the microprocessor ascertains the configuration instructions for a task-specific processor by evaluating the control data in the configuration table,

the microprocessor is designed to configure the task-specific processors by transmitting suitable configuration instructions via the processor interface, and

the first bus is provided for transferring the configuration instructions and the control data.

2. The transmission/reception device as claimed in claim 1 , wherein

the second bus connects the microprocessor, the plurality of task-specific processors and also at least one data storage means in the transmission/reception device to one another for the purpose of data interchange.

3. The transmission/reception device as claimed in claim 2 , wherein

further hardware modules and/or external interfaces for the transmission/reception device are connected to the second bus.

4. The transmission/reception device as claimed in claim 2 , wherein

the plurality of task-specific processors can be connected to the second bus via a configurable interface, and

a configuration instruction transferred via the processor interface by the microprocessor can be used to assign the configurable interface to a particular task-specific processor or to a submodule thereof.

5. The transmission/reception device as claimed in claim 3 , wherein

the plurality of task-specific processors can be connected to the second bus via a configurable interface, and

a configuration instruction transferred via the processor interface by the microprocessor can be used to assign the configurable interface to a particular task-specific processor or to a submodule thereof.

6. The transmission/reception device as claimed in claim 1 , wherein

a first task-specific processor is a RAKE data processing circuit.

7. The transmission/reception device as claimed in claim 6 , wherein the configuration parameters for the RAKE data processing circuit comprise one or more of the following parameters:

operating state of a RAKE finger,

delay offset of a RAKE finger,

scrambling code identifier for a RAKE finger,

delay offset of the scrambling code for a RAKE finger,

spreading code identifier for a RAKE finger, and

spreading factor for a RAKE finger.

8. The transmission/reception device as claimed in claim 1 , wherein

a second task-specific processor is a searcher.

9. The transmission/reception device as claimed in claim 8 , wherein control data provided by the searcher comprise one or more of the following parameters:

levels of the ascertained signal peaks,

delay offsets of the ascertained signal peaks, and

cell identifiers of the ascertained signal peaks.

10. A method for processing data in a transmission/reception device for mobile radio applications for a third or higher generation mobile station, comprising a microprocessor, a plurality of task-specific processors, wherein each task-specific processor can be configured such that a basic function performed by the task-specific processor can be controlled by changing configuration parameters, and a bidirectional processor interface which connects the microprocessor to the task-specific processor, comprising the steps of:

ascertaining the configuration parameters for a task-specific processor by evaluating control data which have been calculated beforehand in another task-specific processor and have been communicated to the microprocessor,

transmitting the configuration instructions and/or control data via a first bus to one task-specific processor, the first bus connecting the processor interface associated with the microprocessor to each task-specific processor,

configuring one task-specific processor by transmitting suitable configuration instructions from the microprocessor to one task-specific processor via the processor interface,

following configuration of one task-specific processor, instructing the latter to process data in line with a function determined by the configuration, and

transmitting further data to be processed from one task-specific processor using a separate second bus, which connects the microprocessor and at least one of the task-specific processors to one another for the purpose of data interchange.

11. The method as claimed in claim 10 , wherein a first task-specific processor is a RAKE data processing circuit, and the configuration step comprises the prescription of one or more of the following parameters:

operating state of a RAKE finger,

delay offset of a RAKE finger,

scrambling code identifier for a RAKE finger,

delay offset of the scrambling code for a RAKE finger,

spreading code identifier for a RAKE finger, and

spreading factor for a RAKE finger.

12. The method as claimed in claim 10 , wherein a second task-specific processor is a searcher, and comprising the following step:

control data from the searcher are transmitted to the microprocessor, said control data comprising one or more of the following parameters:

levels of the ascertained signal peaks,

delay offsets of the ascertained signal peaks, and

cell identifiers of the ascertained signal peaks.

13. The method as claimed in claim 11 , wherein a second task-specific processor is a searcher, and comprising the following step:

control data from the searcher are transmitted to the microprocessor, said control data comprising one or more of the following parameters:

levels of the ascertained signal peaks,

delay offsets of the ascertained signal peaks, and

cell identifiers of the ascertained signal peaks.

14. The method as claimed in claim 10 , wherein

data are processed in a task-specific processor following configuration thereof using a multiplicity of cycles, particularly using a multiplicity of timeslots or timeframes when taking a transmission system with a timeslot and/or timeframe structure as a basis.