RF power amplifier with load insensitive indirect forward power detector

1. An amplifier circuit operable to amplify a radio frequency (RF) input signal to a prescribed power level, comprising:

an isolating gain stage in an adjustable gain amplifier, operable to produce an RF output signal at an output port;

a node in the adjustable gain amplifier isolated from the output port by the isolating gain stage, wherein a signal at the node has a power level that corresponds to the output power level of the RF output signal;

a detector connected to the node, the detector operable to detect the power level of a signal at the node and generate a power level indicator; and

a gain control circuit coupled to the detector, the gain control circuit operable for adjusting the gain of the adjustable gain amplifier in response to the power level indicator,

wherein the adjustable gain amplifier and detector are formed on an integrated circuit.

2. An amplifier circuit as in claim 1 , wherein

the isolating gain stage includes a first transistor, and

the node is isolated from the output port by an internal impedance of the first transistor.

3. An amplifier circuit as in claim 2 , wherein the detector detects the peak voltage at the node.

4. An amplifier circuit as in claim 2 , wherein the detector detects the peak current passing through the node.

5. An amplifier circuit as in claim 2 , wherein the gain control circuit is a comparator comparing the power level indicator to a reference signal to generate a control signal for adjusting the gain of the adjustable gain amplifier.

6. An amplifier circuit as in claim 2 , the adjustable gain amplifier further comprising:

a driver gain stage driving the isolating gain stage.

7. An amplifier circuit as in claim 6 , wherein

the driver gain stage includes a second transistor, and

the node is the drain or collector of the second transistor.

8. An amplifier circuit as in claim 6 , wherein the node is the source or emitter of the second transistor.

9. An amplifier circuit as in claim 1 , wherein the circuit includes a component of the type selected from the group consisting of enhancement-mode pseudomorphic high electron mobility transistors (E-pHEMT), pseudomorphic high electron mobility transistors (pHEMT), heterojunction bipolar transistors (HBT), bipolar junction transistors (BJT), lateral diffusion metal oxide semiconductor field effect transistors (LDMOS FET), metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductors (CMOS), field effect transistors (FET), and metal semiconductor field effect transistors (MESFET).

10. An amplifier circuit as in claim 1 , wherein the RF signal has a frequency greater than 400 megahertz.

11. An amplifier circuit as in claim 1 , wherein the RF signal conforms to a protocol selected from the group consisting of Global System for Mobile Communications (GSM), Enhanced Data rate for GSM Evolution (EDGE), Code Division Multiple Access (CDMA), North American Digital Cellular (NADC), and Wideband Code Division Multiple Access (WCDMA) and Universal Mobile Telecommunications System (UMTS).

12. An amplifier circuit as in claim 1 , further comprising a directional coupler between the node and the detector.

13. A method for maintaining a constant output power for an RF amplifier circuit, comprising:

amplifying an input RF signal with an adjustable gain amplifier;

isolating a node within the adjustable gain amplifier from an output load with an output gain stage;

detecting a signal power level at the node; and

adjusting the gain of the adjustable gain amplifier in response to the signal power level to maintain a constant signal power level at the node into the output gain stage.

14. A method as in claim 13 , wherein

detecting a signal power level includes detecting a peak voltage level.

15. A method as in claim 13 , wherein

detecting a signal power level includes detecting a peak current level.

16. A method as in claim 13 , wherein amplifying an input RF signal includes amplifying with a plurality of cascaded gain stages.

17. A method as in claim 13 , wherein

detecting a signal power level is accomplished by capacitively coupling to the node.

18. A method as in claim 13 , wherein

detecting a signal power level is accomplished by connecting to the node with a direct current (DC) connection.