Semiconductor device, and production method for manufacturing such semiconductor device
View Patent ↗A semiconductor device includes a first conductivity type semiconductor substrate. A first conductivity type drift layer is formed on a surface of the first conductivity type semiconductor substrate, and a second conductivity type base region is produced in the first conductivity type drift layer. The second conductivity type base region has a trench formed in a surface thereof. A trench-stuffed layer is formed by stuffing the trench with a suitable material, and a second conductivity type column region formed in the first conductivity type drift layer and sited beneath the trench-stuffed layer. A first conductivity type source region is produced in the second conductivity type base region, and both a gate insulating layer and a gate electrode layer are produced so as to be associated with the first conductivity type source region and the first conductivity type drift layer such that an inversion region is defined in the second conductivity type base region in the vicinity of both the gate insulating layer and the gate electrode layer.
1. A semiconductor device comprising:
a first conductivity type semiconductor substrate;
a first conductivity type drift layer formed on a surface of said first conductivity type semiconductor substrate;
a second conductivity type base region produced in said first conductivity type drift layer, said second conductivity type base region having a trench formed in a surface thereof;
a trench-stuffed layer formed by stuffing said trench with an insulating material, so that substantially an entirety of said trench is stuffed with said insulating material;
a second conductivity type column region formed in said first conductivity type drift layer and sited entirely beneath a bottom surface of said trench-stuffed layer, a center of said second conductivity type column region being axially aligned with a center of said trench-stuffed layer;
a first conductivity type source region produced in said second conductivity type base region; and
both a gate insulating layer and a gate electrode layer produced so as to be associated with said first conductivity type source region and said first conductivity type drift layer such that an inversion region is defined in said second conductivity type base region in the vicinity of both the gate insulating layer and the gate electrode layer.
2. A semiconductor device as set forth in claim 1 , further comprising:
an insulating interlayer formed on both the gate insulating layer and the gate electrode layer to thereby cover them, a contact hole being perforated in said insulating layer such that said trench-stuffed layer and a part of said first conductivity type source region are exposed;
a source electrode layer formed on said insulating interlayer such that the contact hole is covered with said source electrode layer, to thereby establish an electrical connection between said first conductivity type source region and said source electrode layer; and
a drain electrode layer formed on another surface of said first conductivity type semiconductor substrate.
3. A semiconductor device as set forth in claim 1 , wherein said second conductivity type base region features a depth deeper than that of said trench-stuffed layer.
4. A semiconductor device as set forth in claim 1 , wherein said first conductivity type source region is formed as an annular source region surrounding said trench-stuffed layer in said second conductivity type base region.
5. A semiconductor device as set forth in claim 1 , wherein an axial length of said second conductivity type column region is larger than a depth of said trench.
6. A semiconductor device as set forth in claim 1 , wherein both the gate insulating layer and the gate electrode layer are formed as another trench-stuffed layer buried in said first conductivity type drift layer.
7. A semiconductor device as set forth in claim 1 , wherein said trench-stuffed layer is included in second conductivity type base region.
8. A semiconductor device as set forth in claim 1 , wherein said first conductivity type source region is spaced apart from said trench-stuffed layer.
9. A semiconductor device comprising:
a first conductivity type semiconductor substrate;
a first conductivity type drift layer formed on a surface of said first conductivity type semiconductor substrate;
a second conductivity type base region produced in said first conductivity type drift layer, said second conductivity type base region having a trench formed in a surface thereof;
an insulating material filling substantially an entirety of said trench;
a second conductivity type column region formed in said first conductivity type drift layer and having a center thereof axially aligned with a center of said trench so that an entirety of said column region is beneath a bottom surface of said trench;
a first conductivity type source region produced in said second conductivity type base region; and
both a gate insulating layer and a gate electrode layer formed on said first conductivity type source region and said first conductivity type drift layer.
10. A semiconductor device as set forth in claim 9 , further comprising:
an insulating interlayer covering both the gate insulating layer and the gate electrode layer, a contact hole being in said insulating layer such that said first material and a part of said first conductivity type source region are exposed;
a source electrode layer formed on said insulating interlayer such that the contact hole is covered with said source electrode layer, to thereby establish an electrical connection between said first conductivity type source region and said source electrode layer; and
a drain electrode layer formed on opposing second surface of said first conductivity type semiconductor substrate.
11. A semiconductor device as set forth in claim 9 , wherein said second conductivity type base region features a depth deeper than that of said first material.
12. A semiconductor device as set forth in claim 9 , wherein said first conductivity type source region is formed as an annular source region surrounding said trench in said second conductivity type base region.
13. A semiconductor device as set forth in claim 9 , wherein an axial length of said second conductivity type column region is larger than a depth of said trench.
14. A semiconductor device as set forth in claim 9 , wherein both the gate insulating layer and the gate electrode layer are buried in said first conductivity type drift layer.
15. A semiconductor device as set forth in claim 9 , wherein said insulating material filling said trench is included in second conductivity type base region.
16. A semiconductor device as set forth in claim 9 , wherein said first conductivity type source region is spaced apart from said trench-stuffed layer.
17. A semiconductor device comprising:
a first conductivity type semiconductor substrate;
a first conductivity type drift layer formed on a first surface of said first conductivity type semiconductor substrate;
a second conductivity type base region within said first conductivity type drift layer, said second conductivity type base region having a trench formed therein, substantially an entirety of said trench being filled with an insulating material, a bottom surface of said trench being above a bottom surface of said second conductivity type base region;
a second conductivity type column region formed in said first conductivity type drift layer, said second conductivity type column region extending beneath the bottom surface of said trench of said second conductivity type base region within said first conductivity type drift layer, a center of said second conductivity type column region being axially aligned with a center of said trench;
a first conductivity type source region produced in said second conductivity type base region; and
both a gate insulating layer and a gate electrode layer formed between said first conductivity type source region and said first conductivity type drift layer.
18. A semiconductor device as set forth in claim 17 , further comprising:
a source electrode layer formed so as to cover the insulating material filling said trench, said first conductivity type source region and said first conductivity type drift layer; and
a drain electrode layer formed on a second surface of said first conductivity type semiconductor substrate.
19. A semiconductor device as set forth in claim 17 , wherein an axial length of said second conductivity type column region is larger than a depth of said trench.
20. A semiconductor device as set forth in claim 17 , wherein said first conductivity type source region is formed as an annular source region surrounding the insulating material filling said trench in said second conductivity type base region.
21. A semiconductor device as set forth in claim 17 , wherein both the gate insulating layer and the gate electrode layer are formed as a trench-stuffed layer buried in said first conductivity type drift layer.
22. A semiconductor device as set forth in claim 17 , wherein a width of said second conductivity type column region is wider than that of the insulating material filling said trench.
23. The semiconductor device as set forth in claim 17 , wherein both the gate insulating layer and the gate electrode layer are formed so as to cover a portion of said second conductivity type base region.