IP Library Granted Patent US 7,408,909
Granted Patent B2
US 7,408,909 · App. 10/833,276 · Granted Aug 5, 2008

Method and apparatus to enable multiple receivers

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Quick Facts
Patent No.
US 7,408,909
App. No.
10/833,276
Granted
Aug 5, 2008
Kind
B2
Abstract

Briefly, a wireless communication device that includes a processor to enable a determined number of receivers of a MIMO system according to a value provided with a request to enable the receivers is provided. A method for enabling the receivers of MIMO system is also provided.

Claims (20)

1. An apparatus comprising

a processor to enable a determined number of receivers of a multiple-inputs-multiple-outputs transmitters-receivers system according to a request to enable the determined number of receivers, wherein the processor is able to control a request-to send/clear-to-send network access mechanism,

wherein the request-to send/clear-to-send network access mechanism comprises:

a multiple-in-multiple-out-request-to send frame that includes the request to enable determined number of receivers; and

a multiple-in-multiple-out-clear-to-send frame to acknowledge the multiple-in-multiple-out-request-request-to send frame,

wherein the multiple-in-multiple-out-request-to-send message comprises: a first duration field to block transmission of a legacy station; a second duration field to block a high throughput station; and a multiple-in-multiple-out field that include a number of receivers to be enabled.

2. The apparatus of claim 1 , wherein the first field includes a value composed from a duration of the multiple-in-multiple-out-clear-to-send frame, at least twice a duration of a short inter frame space and an additional duration to overlap with at least a beginning portion of a data sequence transmission.

3. The apparatus of claim 1 wherein, the second field includes a value composed from a duration of the multiple-in-multiple-out-clear-to-send frame, duration of at least two durations of short inter frame space and duration of a data sequence transmission.

4. A wireless communication device comprising:

a processor to enable a determined number of receivers of a multiple-inputs-multiple-outputs transmitters-receivers system according to a request to enable the determined number of receivers; and

two or more dipole antennas operably coupled to two or more transmitters and two or more receivers of the multiple-inputs-multiple-outputs transmitters-receivers system,

wherein the processor is able to control a request-to send/clear-to-send network access mechanism, wherein the request-to send/clear-to-send network access mechanism comprises:

a multiple-in-multiple-out-request-to send frame that includes the request to enable the determined number of receivers, and

a multiple-in-multiple-out-clear-to-send frame to acknowledged the multiple-in-multiple-out-request-to send frame,

wherein the multiple-in-multiple-out-request-to send message comprises: a first duration field to block transmission of a legacy station; a second duration field to block a high Throughput station; and a multiple-in-multiple-out field to enable the determined number receivers.

5. The wireless communication device of claim 4 , wherein the processor is able to control an access to a wireless shared medium according to a network access vector.

6. The wireless communication device of claim 5 , wherein the processor is able to block transmissions of stations other than said legacy station and said high throughout station for a desired time period by providing the blocking time to the network access vector.

7. The wireless communication device of claim 6 , wherein the desired time period is provided by the request to enable the determined number of receivers of the multiple-inputs-multiple-outputs transmitters-receivers system.

8. The wireless communication device of claim 6 , wherein the desired time period is provided by an acknowledgment message.

9. The wireless communication device of claim 6 , wherein the desired time period is set according to a length of a multiple-input-multiple-output transmitted data sequence.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 052414/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2004
From: TRAININ, SOLOMON B.; LEVY, SHMUEL
To: INTEL CORPORATION
Reel/Frame 015709/0966 →