Method of manufacturing a semiconductor integrated circuit device
View Patent ↗Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased. Side wall spacers can be provided on the sides of the gate electrodes of the MISFETs and on the sides of the local wiring lines, and connection holes to semiconductor regions of these MISFETs are self-aligned to both the gate electrodes and the local wiring lines, whereby capacitor area can be increased and integration of the device can also be increased.
1. A semiconductor device, comprising:
a static memory cell including first and second driver MISFETs and first and second load MISFETs, and first and second transfer MISFETs; and
a capacitor element including a first electrode, a dielectric layer, and a second electrode,
wherein gates of said first driver MISFET and said first load MISFET are formed by a first gate layer, and
wherein gates of said second driver MISFET and said second load MISFET are formed by a second gate layer; and
first and second voltage lines, extending in a first direction crossing a second direction in which said first and second gate layers extend,
wherein a third layer forming said first electrode electrically connects the drains of said first driver MISFET and said first load MISFET,
wherein a fourth layer forming said second electrode electrically connects the drains of said second driver MISFET and said second load MISFET,
wherein said third layer is formed between said first gate layer and said fourth layer,
wherein a size of said fourth layer is larger than a size of said third layer,
wherein said first and second voltage lines are metal layers, and
wherein said fourth layer comprises a tungsten layer.
2. The semiconductor device according to claim 1 , wherein said fourth layer completely covers said third layer.
3. The semiconductor device according to claim 2 , wherein said dielectric layer includes a silicon nitride film.