Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device, comprising:

a plurality of memory cells, each of which includes:

a first conductive type of semiconductor substrate;

first and second diffusion layers formed on the semiconductor substrate, the diffusion layers being of a second conductive type;

a channel region formed between the first and second diffusion layers;

a gate insulating layer formed on the channel region;

a gate electrode formed on the gate insulating layer;

a first variable resistance region, which is formed outside the first diffusion layer and is of the second conductive type;

a second variable resistance region, which is formed outside the second diffusion layer and is of the second conductive type;

wherein a couple of bits of data are stored in the memory cell, the stored data being controlled according to resistance values of the first and second variable resistance regions,

wherein one of the memory cells shares its first diffusion layer with an adjacent memory cell and shares its second diffusion layer with another adjacent memory cell,

wherein the first diffusion layers of the plurality of memory cells are coupled to each other with a first conductive line extending in a first direction,

wherein the second diffusion layers of the plurality of memory cells are coupled to each other with a second conductive line extending in the first direction, and

wherein the gate electrodes of the plurality of memory cells are coupled to each other with a third conductive line extending in a second direction, which is orthogonal to the first direction.

2. A nonvolatile semiconductor memory device according to claim 1 , wherein

each of the plurality of memory cells further comprises first and second charge storage regions formed on the first and second variable resistance regions, respectively so that resistance values of the first and second variable resistance regions are controlled by changing amounts of electric charge in the first and second charge storage regions, respectively.

3. A nonvolatile semiconductor memory device according to claim 2 , wherein

each of the first and second charge storage regions is of a O—N—O insulating layer.

4. A nonvolatile semiconductor memory device according to claim 1 , wherein

the first and second conductive types are P-type and N-type, respectively.

5. A nonvolatile semiconductor memory device according to claim 4 , wherein

the third conductive line is a word line.

6. A nonvolatile semiconductor memory device according to claim 5 , further comprising:

a side wall, provided on a side of and along the word line.

7. A nonvolatile semiconductor memory device according to claim 1 , wherein

the first and second conductive lines are bit lines.

8. A nonvolatile semiconductor memory device according to claim 1 , wherein

the first and second resistance variable regions are N-type diffusion layers.

9. A nonvolatile semiconductor memory device according to claim 1 , further comprising:

a side wall, provided on a side of the gate electrode.

10. A nonvolatile semiconductor memory device according to claim 9 , wherein

the side wall is provided along the third conductive line.

11. A nonvolatile semiconductor memory device, comprising:

a plurality of memory cells, each of which includes:

a first conductive type of semiconductor substrate;

first and second diffusion layers formed on the semiconductor substrate, the diffusion layers being of a second conductive type;

a channel region formed between the first and second diffusion layers;

a gate insulating layer formed on the channel region;

a gate electrode formed on the gate insulating layer;

a first variable resistance region, which is formed outside the first diffusion layer and is of the second conductive type;

a second variable resistance region, which is formed outside the second diffusion layer and is of the second conductive type;

first and second charge storage regions formed on the first and second variable resistance regions, respectively so that resistance values of the first and second variable resistance regions are controlled by changing amounts of electric charge in the first and second charge storage regions, respectively;

wherein a couple of bits of data are stored in the memory cell, the stored data being controlled according to resistance values of the first and second variable resistance regions,

wherein one of the plurality of memory cells shares its first diffusion layer with an adjacent memory cell and shares its second diffusion layer with another adjacent memory cell,

wherein the first diffusion layers of the plurality of memory cells are coupled to each other with a first bit line extending in a first direction,

wherein the second diffusion layers of the plurality of memory cells are coupled to each other with a second bit line extending in the first direction, and

wherein the gate electrodes of the plurality of memory cells are coupled to each other with a word line extending in a second direction, which is orthogonal to the first direction.

12. A nonvolatile semiconductor memory device according to claim 11 , wherein

each of the first and second charge storage regions is of a O—N—O insulating layer,

the first and second resistance variable regions are N-type diffusion layers.

13. A nonvolatile semiconductor memory device according to claim 11 , further comprising:

a side wall, provided on a side of and along the word line.