Low noise op amp
View Patent ↗The present invention relates amplifiers using metal oxide semiconductor based integrated circuits. The present invention is particularly but not exclusively related to audio application mixed signal chips. The present invention provides an analog circuit for processing analog signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices, the circuit stage comprising a first said transistor device having a first oxide thickness, and a second said transistor device having a second and different oxide thickness. Preferably a cascode based op amp structure is implemented.
1. An analogue circuit for processing analogue signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices, the circuit stage comprising:
a first said transistor device having a first oxide thickness and arranged in use to have an operating voltage below a predetermined level;
a second said transistor device having a second greater oxide thickness arranged such that in use it is not constrained by the predetermined operating voltage level; and
a clamp circuit arranged to limit the operating voltage such that the voltage between the drain and source of said first transistor is limited to the predetermined operating voltage level.
2. A circuit according to claim 1 wherein the predetermined operating voltage level is 3.6V and the first oxide thickness is 70 nm.
3. A circuit according to claim 1 wherein the second transistor device forms part of a cascode transistor device circuit within said analogue circuit.
4. A circuit according to claim 3 wherein the cascode transistor device circuit is a differential folded cascode op amp circuit.
5. A circuit according to claim 4 wherein the op amp circuit further comprises input, bias, current mirror and constant current sub-circuits and wherein said first transistor device forms part of one of said op amp sub-circuits.
6. A mixed signal integrated circuit comprising an analogue circuit for processing analogue signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices, the circuit stage comprising:
a first said transistor device having a first oxide thickness and arranged in use to have an operating voltage below a predetermined level;
a second said transistor device having a second greater oxide thickness arranged such that in use it is not constrained by the predetermined operating voltage level; and
a clamp circuit arranged to limit the operating voltage such that the voltage between the drain and source of said first transistor is limited to the predetermined operating voltage level.
7. A method of processing an analogue signal comprising applying the analogue signal to an analogue circuit for processing analogue signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices, the analogue circuit comprising:
a first said transistor device having a first oxide thickness and arranged in use to have an operating voltage below a predetermined level;
a second said transistor device having a second greater oxide thickness arranged such that in use it is not constrained by the predetermined operating voltage level; and
a clamp circuit arranged to limit the operating voltage such that the voltage between the drain and source of said first transistor is limited to the predetermined operating voltage level, wherein the analogue signal is processed by both said transistor devices.
8. A method according to claim 7 wherein the second transistor device forms part of a cascode transistor device circuit within said analogue circuit.
9. A method of producing an analogue circuit for processing analogue signals in an integrated circuit; the method comprising:
providing a number of metal oxide semiconductor transistor devices arranged to implement said analogue circuit, at least a first said transistor device having a first oxide thickness and arranged in use to have an operating voltage below a predetermined level, and at least a second said transistor device having a second greater oxide thickness and arranged such that in use it is not constrained by the predetermined operating voltage level; and
providing a clamp circuit arranged to limit the operating voltage such that the voltage between the drain and source of said first transistor is limited to the predetermined operating voltage level.
10. A method according to claim 9 further comprising providing a second number of metal oxide semiconductor transistors devices arranged to implement a digital circuit.