Low dropout voltage regulator providing adaptive compensation
View Patent ↗A method and apparatus to dynamically modify internal compensation of a low dropout (LDO) voltage regulator is provided. The LDO voltage regulator includes an output pass transistor, an error amplifier, a bias transistor and a compensation network. The compensation network is connected between a gate and a drain of the output pass transistor to compensate for the feedback loop. The compensation network and the bias transistor generate pole-zero pairs to perform a maximum 45 degrees phase shift before reaching the crossover frequency in the LDO voltage regulator. Therefore a minimum 45 degrees phase margin is provided for the feedback loop in various load conditions. Furthermore, the pole-zero pairs produced in the LDO voltage regulator are adaptively adjusted according to load conditions, so that the bandwidth is optimized and faster transient response is achieved.
1. A low dropout voltage regulator comprising:
an unregulated DC input terminal;
a regulated DC output terminal, supplying an output current to an output load, wherein said output load is coupled from said regulated DC output terminal to a reference ground level;
an output pass transistor, supplying power to said regulated DC output terminal, wherein said output pass transistor has a source coupled to said unregulated DC input terminal, and said output pass transistor has a drain connected to said regulated DC output terminal;
an error amplifier, for controlling a gate of said output pass transistor;
a bias transistor, coupled between an output of said error amplifier and said gate of said output pass transistor, wherein a drain of said bias transistor is coupled to said gate of said output pass transistor;
a compensation network, coupled between said gate and said drain of said output pass transistor for frequency compensation;
a mirror transistor, for generating a mirror current in proportion to said output current, wherein a source of said mirror transistor is coupled to said source of said output pass transistor, wherein a gate of said mirror transistor is coupled to said gate of said output pass transistor, wherein said mirror current is generated form a drain of said mirror transistor;
a first programmable current source, generating a first-mirror current in proportion to said mirror current;
a first-mirror transistor, for programming the impedance of said compensation network in response to said first-mirror current, wherein a gate and a drain of said first-mirror transistor are coupled to each other to form a current mirror, wherein said drain of said first-mirror transistor is coupled to said first programmable current source;
a second programmable current source, generating a second-mirror current in proportion to said mirror current; and
a second-mirror transistor, for programming the impedance of said bias transistor in response to said second-mirror current, wherein a source of said second-mirror transistor and a source of said bias transistor are coupled to said output of said error amplifier, wherein a gate of said bias transistor, a gate of said second-mirror transistor and a drain of said second-mirror transistor are coupled to said second programmable current source.
2. The low dropout voltage regulator as recited in claim 1 , wherein the impedance of said bias transistor is inversely proportional to said output current.
3. The low dropout voltage regulator as recited in claim 1 , wherein said compensation network comprises:
a first slice, having a first capacitor and a first transistor coupled to each other in series, wherein said first capacitor is coupled between said gate of said output pass transistor and a drain of said first transistor, wherein a source of said first transistor is coupled to said drain of said output pass transistor;
a second slice, coupled to said first transistor in parallel, wherein said second slice comprises a second capacitor and a second transistor coupled to each other in series; and
a distribution network, having a plurality of capacitors and transistors coupled to said second transistor in parallel, wherein sources of said first-mirror transistor, said first transistor, said second transistor and transistors in said distribution network are coupled to said drain of said output pass transistor, wherein gates of said first transistor, second transistor and transistors in said distribution network are coupled to said gate of said first-mirror transistor.
4. The low dropout voltage regulator according to claim 1 , wherein the impedance of said first transistor, said second transistor, and transistors in said distribution network are associated with the impedance of said first-mirror transistor.
5. The low dropout regulator as recited in claim 1 , wherein the impedance of said first transistor, said second transistor, and transistors in said distribution network are inversely proportional to said output current.
6. The low dropout voltage regulator as recited in claim 1 , wherein said compensation network and said bias transistor generate a plurality of pole-zero pairs for frequency compensation, wherein frequencies of said pole-zero pairs increase as said output current increase for obtaining prompt transient response.