Differential sense amplifier latch for high common mode input
View Patent ↗A sense amplifier latch that is operable to interface with high common-mode input voltages with wide ranges for all process variations. The sense amplifier latch comprises a cross-coupled latch having first and second rail signals; a pre-charge device; an equalization device; pass devices for enabling input devices to receive pad and reference inputs. In the present invention, the input devices comprise push-pull impedance dividers are used to preserve the input difference voltage while dramatically lowering the common-mode output voltage. The outputs of the impedance dividers are fed to the cross-coupled latch of the sense amplifier using n-channel pass gates.
1. A sense amplifier latch, comprising:
a latch module operable to generate first and second rail signals;
a precharge and equalization module;
an impedance divider network comprising a plurality of MOS devices connected in a push-pull configuration, said impedance divider network having a plurality of input ports operable to receive first and second input signals;
first and second pass gates operable to control operation of said impedance divider network to receive one of said first and second input signals;
the impedance divider network comprising first and second MOS devices in a first push pull configuration, the first push pull configuration operable to receive the other of the first and second input signals and a reference signal, and third and fourth MOS devices in a second push pull configuration, the second push pull configuration operable to receive the other of the first and second input signals and said reference signal;
a first output of the first push pull configuration coupled with the first pass gate, the first pass gate coupled with the first rail signal;
a second output of the second push pull configuration coupled with the second pass gate, the second pass gate coupled with the second rail signal;
wherein said first and second rail signals are initially precharged to Vdd and thereafter are pulled down to a predetermined voltage level in response to said first and second input signals; and
wherein, said MOS devices in said impedance divider network have substantially identical feature sizes and are operable to maintain a difference between said first and second input signals, while maintaining a common mode output voltage at a predetermined level.
2. The sense amplifier according to claim 1 , wherein said plurality of MOS devices comprise thick-oxide MOS transistors.
3. The sense amplifier according to claim 2 , wherein said impedance divider network comprises four n-channel MOS devices, wherein two of said MOS devices receive the other the said first and second input signals and two of said MOS devices receive said reference signal.
4. The sense amplifier according to claim 3 , wherein the outputs of said MOS devices are communicated to said latch module by said first and second pass gates.
5. A method of generating output signals from a sense amplifier latch, comprising:
receiving a first and a second input signal in an impedance divider network comprising a plurality of MOS devices connected in a push-pull configuration, said impedance divider network having a plurality of input ports operable to receive one of said first and second input signals and a reference signal, the impedance divider network comprising first and second MOS devices in a first push pull configuration, the first push pull configuration operable to receive the one of first and second input signals and said reference signal, and third and fourth MOS devices in a second push pull configuration, the second push pull configuration operable to receive one of the first and second input signals and said reference signal;
using a first and a second pass gate to control operation of said impedance divider network to receive the other of said first and second input signals and to generate output signals therefrom the first pass gate communicating with a first rail output signal, the second pass gate communicating with a second rail output signal; and
using a latch module to process said output signals from said impedance divider to generate the first and second rail output signals corresponding to a difference in said first and second input signals;
wherein said first and second rail signals are initially precharged to Vdd and thereafter are pulled down to a predetermined level in response to said first and second input signals; and
wherein, said MOS devices in said impedance divider network having substantially identical feature sizes and are operable to maintain a difference between said first and second input signals, while maintaining a common mode output voltage at a predetermined level.
6. The method according to claim 5 , wherein said MOS devices comprise thick-oxide MOS transistors.
7. The method according to claim 6 , wherein said impedance divider network comprises four n-channel MOS devices, wherein two of said MOS devices receive one of said first and second input signals and two of said MOS devices receive said reference signal.
8. The method according to claim 7 , wherein the outputs of said MOS devices are communicated to said latch module by said first and second pass gates.