Method and apparatus for detecting the position of light which is incident to a semiconductor die

1. A method for detecting light which is incident to a first semiconductor die to facilitate in aligning the first semiconductor die, the method comprising:

biasing a gate voltage of an integrating transistor to be close to a threshold voltage of the integrating transistor;

generating light from a light source located on a second semiconductor die which is in close proximity to the first semiconductor die, so that the light is received at the photo-detector on the first semiconductor die;

receiving the light at a photo-detector on the first semiconductor die, wherein the photo-detector converts the received light into a current;

applying the current to the gate of the integrating transistor so that the current causes a charge to collect at the gate of the integrating transistor, which eventually causes the integrating transistor to switch, thereby indicating that light has been received by the photo-detector on the first semiconductor die;

receiving light at a second photo-detector on the first semiconductor die, wherein the second photo-detector is part of an array of photo-detectors on the first semiconductor die;

applying the current from the second photo-detector to a corresponding integrating transistor in a corresponding array of integrating transistors; and

determining an alignment of the first semiconductor die relative to the second semiconductor die based upon which photo-detectors in the array of photo-detectors received the light, wherein the alignment is to a precision that would allow capacitive communication between the first semiconductor die and the second semiconductor die.

2. The method of claim 1 ,

wherein the integrating transistor switching causes a detector output to switch;

wherein the method further involves storing detector outputs from the array of integrating transistors into an output register;

wherein the output register indicates which photo-detectors in the array of photo-detectors received light.

3. The method of claim 1 , wherein the photo-detector includes:

a photo-diode; or

a P/N-junction photo-detector.

4. The method of claim 1 , wherein the light is generated by one of:

a Zener diode;

a light emitting diode (LED);

a vertical cavity surface emitting laser (VCSEL); and

an avalanche breakdown P/N diode.

5. An apparatus for detecting light which is incident to a first semiconductor die to facilitate in aligning the first semiconductor die, comprising:

a biasing mechanism configured to bias a gate voltage of an integrating transistor to be close to a threshold voltage of the integrating transistor;

a light-generating mechanism configured to generate light from a light source located on a second semiconductor die which is in close proximity to the first semiconductor die, so that the light is received at the photo-detector on the first semiconductor die;

a receiving mechanism configured to receive the light at a photo-detector on the first semiconductor die, wherein the photo-detector converts the received light into a current;

wherein the receiving mechanism is configured to apply the current to the gate of the integrating transistor, so that the current causes a charge to collect at the gate of the integrating transistor, which eventually causes the integrating transistor to switch, thereby indicating that light has been received by the photo-detector on the first semiconductor die;

a second receiving mechanism configured to receive light at a second photo-detector on the first semiconductor die, wherein the second photo-detector is part of an array of photo-detectors on the first semiconductor die;

wherein the second receiving mechanism is configured to apply the current from the second photo-detector to a corresponding integrating transistor in a corresponding array of integrating transistors; and

an alignment mechanism configured to determine an alignment of the first semiconductor die relative to the second semiconductor die based upon which photo-detectors in the array of photo-detectors received the light, wherein the alignment is to a precision that would allow capacitive communication between the first semiconductor die and the second semiconductor die.

6. The apparatus of claim 5 ,

wherein the integrating transistor switching causes a detector output to switch;

wherein the apparatus further comprises an output register configured to store detector outputs from the array of integrating transistors;

wherein the output register indicates which photo-detectors in the array of photo-detectors received light.

7. The apparatus of claim 5 , wherein the photo-detector includes:

a photo-diode; and

a P/N-junction photo-detector.

8. The apparatus of claim 5 , wherein the light is generated by one of:

a Zener diode;

a light emitting diode (LED);

a vertical cavity surface emitting laser (VCSEL); and

an avalanche breakdown P/N diode.

9. A computer system including a mechanism for aligning a first semiconductor die based on light incident to the first semiconductor die, comprising:

a processor;

a memory;

the first semiconductor die comprising at least one of the processor and the memory;

a biasing mechanism on the first semiconductor die configured to bias a gate voltage of an integrating transistor to be close to a threshold voltage of the integrating transistor;

a light-generating mechanism configured to generate light from a light source located on a second semiconductor die which is in close proximity to the first semiconductor die, so that the light is received at the photo-detector on the first semiconductor die;

a receiving mechanism configured to receive the light at a photo-detector on the first semiconductor die, wherein the photo-detector converts the received light into a current

wherein the receiving mechanism is configured to apply the current to the gate of the integrating transistor, so that the current causes a charge to collect at the gate of the integrating transistor, which eventually causes the integrating transistor to switch, thereby indicating that light has been received by the photo-detector on the first semiconductor die;

a second receiving mechanism configured to receive light at a second photo-detector on the first semiconductor die, wherein the second photo-detector is part of an array of photo-detectors on the first semiconductor die;

wherein the second receiving mechanism is configured to apply the current from the second photo-detector to a corresponding integrating transistor in a corresponding array of integrating transistors; and

an alignment mechanism configured to determine an alignment of the first semiconductor die relative to the second semiconductor die based upon which photo-detectors in the array of photo-detectors received the light, wherein the alignment is to a precision that would allow capacitive communication between the first semiconductor die and the second semiconductor die.

10. The computer system of claim 9 ,

wherein the integrating transistor switching causes a detector output to switch;

wherein the apparatus further comprises an output register configured to store detector outputs from the array of integrating transistors;

wherein the output register indicates which photo-detectors in the array of photo-detectors received light.

11. The computer system of claim 9 , wherein the photo-detector includes:

a photo-diode; and

a P/N-junction photo-detector.

12. The computer system of claim 9 , wherein the light is generated by one of:

a Zener diode;

a light emitting diode (LED);

a vertical cavity surface emitting laser (VCSEL); and

an avalanche breakdown P/N diode.