Associative memory device
View Patent ↗An associative memory support for a data processing system includes an associative memory device containing n-cells. A controller is provided for issuing an instruction to the associative memory device. A clock device outputs a synchronizing clock signal that includes a predetermined number of clock cycles per second, the clock device outputting the synchronizing clock signal to the associative memory device and the controller. The controller globally communicates the instruction to all of the n-cells simultaneously, within one of the clock cycles and the instruction is applied equally to each of the n-cells.
1. A data processing system comprising:
an associative memory device containing n-cells, wherein n is any known whole number greater than zero;
a controller for issuing a command to said n-cells in said associative memory device; and
wherein said command defines a size and location of a key field within each of said n-cells, said key field being utilized to identify data within said n-cells.
2. An associative memory system for data processing, said associative memory system comprising:
an associative memory device containing n-cells, n being any known whole number greater than zero;
a controller for issuing an instruction to said n-cells; and
wherein said instruction defines a size of a key field utilized in an execution of said instruction.
3. The associative memory system for data processing system according to claim 2 , wherein:
said defined size of said key field is applied to all of said n-cells.
4. An associative memory system for data processing, said associative memory system comprising:
an associative memory device containing n-cells, n being any known whole number greater than zero, and wherein each of said n-cells stores m-bits of data therein, m being any known whole number greater than zero;
a controller for issuing an instruction to said n-cells; and
wherein said instruction selectively defines which of said m-bits within each of said n-cells represents a key field for each of said n-cells.
5. An associative memory system for data processing, said associative memory system comprising:
an associative memory device containing n-cells, each of said n-cells storing m-bits of data, wherein n and m are any known whole number greater than zero;
a controller for issuing an instruction to said n-cells; and
wherein said instruction selectively designates which of said m-bits within each of said n-cells is to act as a key field in accordance with said issued instruction.