Method and/or apparatus implemented in hardware to discard bad logical transmission units (LTUs)

1. An apparatus comprising:

a logic circuit configured to generate a check signal in response to a data signal decoded from a series of frames, each of said frames comprising a plurality of logical transmission units (LTUs), each of said LTUs comprising (a) a payload and (b) a field;

a compare circuit configured to generate a compare signal in response to said check signal and said field corresponding to each of said LTUs in said data signal;

a control circuit configured to generate a control signal indicating either a valid status or an invalid status of each of said payloads in response to a data valid signal and said compare signal, wherein said control signal indicates said invalid status when said data valid signal indicates a frame error and said compare signal indicates said invalid status; and

a memory interface configured to generate an output data signal in response to said control signal, wherein said memory interface (i) stores each of said payloads when received and (ii) overwrites at least one of said payloads having said invalid status such that said payloads have a different sequence as stored than as in said frame.

2. The apparatus according to claim 1 , wherein said memory interface is further configured to generate a count signal indicating a number of said payloads having said valid status stored in said memory interface.

3. The apparatus according to claim 1 , wherein said plurality of said LTUs are configured as service data units (SDUs).

4. The apparatus according to claim 1 , further comprising a processing circuit configured to process said payloads prior to storage in said memory interface.

5. The apparatus according to claim 1 , wherein said memory interface comprises:

a memory comprising a plurality of addresses;

an address counter configured to count a first number of said addresses used;

an LTU counter configured to count a second number of valid LTUs; and

an address register configured to store a base address.

6. The apparatus according to claim 1 , wherein said logic circuit comprises a cyclical redundancy check (CRC) logic circuit.

7. The apparatus according to claim 1 , wherein said logic circuit comprises a finite state machine.

8. The apparatus according to claim 1 , wherein said check signal comprises a multi-bit signal and said data valid signal comprises a single-bit signal.

9. The apparatus according to claim 1 , wherein said apparatus is implemented in a code division multiple access (CDMA) chipset.

10. The apparatus according to claim 1 , wherein said apparatus is implemented in hardware.

11. The apparatus according to claim l, wherein (i) said check signal comprises a calculated cyclical redundancy check (CRC) data signal and (ii) said field comprises a CRC word.

12. An apparatus comprising:

means for generating a check signal in response to a data signal decoded from a series of frames, each of said frames comprising a plurality of logical transmission units (LTUs), each of said LTUs comprising (a) a payload and (b) a field;

means for generating a compare signal in response to said check signal and said field corresponding to each of said LTUs in said data signal;

means for generating a control signal indicating either a valid status or an invalid status of each of said payloads in response to a data valid signal and said compare signal, wherein said control signal indicates said invalid status when said data valid signal indicates a frame error and said compare signal indicates said invalid status; and

means for generating an output data signal in response to said control signal, wherein said output data signal generating means (i) stores each of said Payloads when received and (ii) overwrites at least one of said payloads having said invalid status such that said payloads have a different sequence as stored than as in said frame.

13. The apparatus according to claim 12 , wherein (i) said check signal comprises a calculated cyclical redundancy check (CRC) data signal and (ii) said field comprises a CRC word.

14. A method for using hardware to discard bad logical transmission units, comprising the steps of:

(A) generating a check signal in response to a data signal decoded from a series of frames, each of said frames comprising a plurality of logical transmission units (LTUs), each of said LTUs comprising (a) a payload and (b) a field;

(B) generating a compare signal in response to said check signal and said field corresponding to each of said LTUs in said data signal;

(C) generating a control signal indicating either a valid status or an invalid status of each of said payloads in response to a data valid signal and said compare signal, wherein said control signal indicates said invalid status when said data valid signal indicates a frame error and said compare signal indicates said invalid status; and

(D) generating an output data signal in response to said control signal by (i) storing each of said payloads when received and (ii) overwriting at least one of said payloads having said invalid status such that said payloads have a different sequence as stored than as in said frame.

15. The method according to claim 14 , wherein (i) said check signal comprises a calculated cyclical redundancy check (CRC) data signal and (ii) said field comprises a CRC word.