Semiconductor memory device with row selection control circuit
View Patent ↗A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.
1. A semiconductor memory device comprising:
a memory array including a plurality of memory cells arranged in a matrix;
a command detection circuit providing a command detection signal indicating that an access command has been applied to said memory array and an internal command signal corresponding to said access command; and
a row selection control circuit carrying out an operation related to row selection of said memory array according to said internal command signal,
said row selection control circuit including
a retain circuit accepting an applied row address according to said command detection signal to retain the applied row address as an internal row address, and
a comparison circuit comparing said row address with said internal row address at an elapse of a first predetermined time upon detection of change in said row address to determine whether said internal row address is to be used in row selection of said memory array.
2. The semiconductor memory device according to claim 1 , wherein said comparison circuit comprises
an address change detection circuit detecting a change in said row address,
a delay circuit delaying an output of said address change detection circuit for said first predetermined time, and
an address comparison unit comparing said row address with said internal row address according to an output of said delay circuit.
3. The semiconductor memory device according to claim 2 , wherein said address comparison unit designates said retain circuit to accept again said row address when a result of address comparison corresponds to mismatch.
4. The semiconductor memory device according to claim 1 , wherein said comparison circuit designates said retain circuit to accept again said row address when said row address does not match said internal row address,
wherein said row selection control circuit further includes a delay circuit inhibiting update of said internal row address to said retain circuit at an elapse of a second predetermined time in response to said command detection signal.
5. The semiconductor memory device according to claim 4 , wherein said second predetermined time is half a basic cycle time which is a period of time starting from said semiconductor memory device receiving said access command up to receiving the next access command.