Thin film transistor array gate electrode for liquid crystal display device
View Patent ↗The present invention discloses a TFT array substrate that is fabricated using a four-mask process and a method of manufacturing that TFT array substrate. The gate line and gate electrode of the array substrate is surrounded by the metallic oxide after finishing a first mask process using thermal treatment. As a result, the gate line and gate electrode are not eroded and damaged by the etchant and stripper during a fourth mask process. Further, buffering layer can optionally be formed between the substrate and the gate line and gate electrode. Thus, silicon ions and oxygen ions included in the substrate are not diffused into the gate line and electrode. Accordingly, the line defect such as a line open of the gate line and gate electrode is prevented, thereby preventing inferior goods while increasing the manufacturing yield.
1. A method of forming a TFT array substrate for use in a liquid crystal display device, comprising:
forming a first metal layer over a substrate;
forming a second metal layer on the first metal layer;
patterning the first and second metal layers so as to form a gate line and a gate electrode;
thermally-treating the substrate having the patterned first and second metal layers so as to diffuse material from the patterned first metal layer over the patterned second metal layer and then to form a metallic oxide layer surrounding the second metal layer by oxidizing the diffused material of the first metal layer;
forming a gate insulation layer on the substrate, the gate line and the metallic oxide layer;
forming an amorphous silicon layer on the gate insulation layer;
forming an impurity-doped amorphous silicon layer on the amorphous silicon layer;
forming a third metal layer on the impurity-doped amorphous silicon layer;
patterning the third metal layer so as to form a data line, a source electrode and a drain electrode;
patterning the impurity-included amorphous silicon layer using the patterned third metal layer as masks so as to form an ohmic contact layer and a channel region in the amorphous silicon layer between the source and drain electrodes;
forming a protection layer on the amorphous silicon layer and on the patterned third metal layer;
patterning the protection layer, the amorphous silicon layer and the gate insulation layer except portions that correspond to the patterned third metal layer and channel region;
depositing a transparent conductive material in a pixel region that is defined by the gate and data lines; and
patterning the transparent conductive material so as to form a pixel electrode that contacts the drain electrode.
2. The method according to claim 1 , wherein the first metal layer is one of tantalum (Ta), chromium (Cr), titanium (Ti) or tungsten (W).
3. The method according to claim 2 , wherein the metallic oxide layer is one of tantalum oxide (TaO X ), chromium oxide (CrO X ), titanium oxide (TiO X ) or tungsten oxide (WO X ).
4. The method according to claim 1 , wherein the third metal layer is one of chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W) or molybdenum (Mo).
5. The method according to claim 1 , further comprising:
forming a buffering layer on the substrate before forming the first metal layer.
6. The method according to claim 5 , wherein the buffering layer is one of silicon nitride (SiN X ) or silicon oxide (SiO 2 ).
7. The method according to claim 1 , wherein thermal treatment of the substrate is performed at a temperature of greater than 400° C.
8. A method of forming a TFT array substrate for use in a liquid crystal display device, comprising:
forming a first metal layer over a substrate;
forming a second metal layer of copper (Cu) on the first metal layer;
patterning the first and second metal layers so as to form a gate line and a gate electrode;
thermally-treating the substrate having the patterned first and second metal layers so as to diffuse material from the patterned first metal layer over the patterned second metal layer and then to form a metallic oxide layer surrounding the second metal layer by oxidizing the diffused material of the first metal layer;
forming a gate insulation layer on the substrate, the gate line and the metallic oxide layer;
forming an amorphous silicon layer on the gate insulation layer;
forming an impurity-doped amorphous silicon layer on the amorphous silicon layer;
forming a third metal layer on the impurity-doped amorphous silicon layer;
patterning the third metal layer so as to form a data line, a source electrode and a drain electrode;
patterning the impurity-included amorphous silicon layer using the patterned third metal layer as masks so as to form an ohmic contact layer and a channel region in the amorphous silicon layer between the source and drain electrodes;
forming a protection layer on the amorphous silicon layer and on the patterned third metal layer;
patterning the protection layer, the amorphous silicon layer and the gate insulation layer except portions that correspond to the patterned third metal layer and channel region;
depositing a transparent conductive material in a pixel region that is defined by the gate and data lines; and
patterning the transparent conductive material so as to form a pixel electrode that contacts the drain electrode.
9. A method of forming a TFT array substrate for use in a liquid crystal display device, comprising:
forming a buffering layer on a substrate, the buffering layer being one of tantalum nitride (TaN) or titanium nitride (TiN);
forming a first metal layer over the buffering layer;
forming a second metal layer on the first metal layer;
patterning the first and second metal layers so as to form a gate line and a gate electrode;
thermally-treating the substrate having the patterned first and second metal layers so as to diffuse material from the patterned first metal layer over the patterned second metal layer and then to form a metallic oxide layer surrounding the second metal layer by oxidizing the diffused material of the first metal layer;
forming a gate insulation layer on the substrate, the gate line and the metallic oxide layer;
forming an amorphous silicon layer on the gate insulation layer;
forming an impurity-doped amorphous silicon layer on the amorphous silicon layer;
forming a third metal layer on the impurity-doped amorphous silicon layer;
patterning the third metal layer so as to form a data line, a source electrode and a drain electrode;
patterning the impurity-included amorphous silicon layer using the patterned third metal layer as masks so as to form an ohmic contact layer and a channel region in the amorphous silicon layer between the source and drain electrodes;
forming a protection layer on the amorphous silicon layer and on the patterned third metal layer;
patterning the protection layer, the amorphous silicon layer and the gate insulation layer except portions that correspond to the patterned third metal layer and channel region;
depositing a transparent conductive material in a pixel region that is defined by the gate and data lines; and
patterning the transparent conductive material so as to form a pixel electrode that contacts the drain electrode.
10. A method of forming an insulated conductor structure for use in a TFT array substrate of a liquid crystal display device, the method comprising:
providing a substrate;
forming a first metal layer over a substrate;
forming a second metal layer on the first metal layer;
patterning the first and second metal layers so as to form a conductive line and a conductive electrode thus defining an intermediate structure;
thermally treating said intermediate structure so as to diffuse material from the patterned first metal layer over the patterned second metal layer and then to form a metallic oxide layer surrounding the patterned second metal layer; and
forming an insulation layer on the substrate, the conductive line and said metallic oxide layer.
11. The method according to claim 10 , wherein the first metal layer is one of tantalum (Ta), chromium (Cr), titanium (Ti) or tungsten (W) and the metallic oxide is one of tantalum oxide (TaO X ), chromium oxide (CrO X ), titanium oxide (TiO X ) or tungsten oxide (WO X ), respectively.
12. The method according to claim 10 , further comprising:
forming a buffering layer on the substrate before forming the first metal layer.
13. The method according to claim 12 , wherein the buffering layer is one of tantalum nitride (TaN), titanium nitride (TiN), silicon nitride (SiN X ) or silicon oxide (SiO 2 ).
14. A method of forming an insulated conductor structure for use in a TFT array substrate of a liquid crystal display device, the method comprising:
providing a substrate;
forming a first metal layer over a substrate;
forming a second metal layer of copper (Cu) on the first metal layer;
patterning the first and second metal layers so as to form a conductive line and a conductive electrode thus defining an intermediate structure;
thermally treating said intermediate structure so as to diffuse material from the patterned first metal layer over the patterned second metal layer and then to form a metallic oxide layer surrounding the patterned second metal layer; and
forming an insulation layer on the substrate, the conductive line and said metallic oxide layer.