Method of fabricating bottom-gated polycrystalline silicon thin film transistor
View Patent ↗A method of forming a thin film transistor includes forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an amorphous silicon layer on the gate insulating layer, crystallizing the amorphous silicon layer within an active region corresponding to the gate electrode to form a polycrystalline silicon layer, etching the amorphous silicon layer such that an etch rate of amorphous silicon is greater than an etch rate of polycrystalline silicon to form a semiconductor layer of polycrystalline silicon in the active region, and forming source and drain electrodes on the semiconductor layer.
1. A method of forming a thin film transistor, comprising:
forming a gate electrode on a substrate;
forming a gate insulating layer on the gate electrode;
forming an amorphous silicon layer on the gate insulating layer;
crystallizing the amorphous silicon layer within an active region corresponding to the gate electrode to form a polycrystalline silicon layer;
etching the amorphous silicon layer such that an etch rate of amorphous silicon is greater than an etch rate of polycrystalline silicon to form a semiconductor layer of polycrystalline silicon in the active region; and
forming source and drain electrodes on the semiconductor layer.
2. The method according to claim 1 , wherein the forming an amorphous silicon layer includes forming an intrinsic amorphous silicon layer on the gate insulating layer and forming an impurity-doped amorphous silicon layer on the intrinsic amorphous silicon layer.
3. The method according to claim 2 , wherein the semiconductor layer includes an active layer of intrinsic polycrystalline silicon and an ohmic contact layer of impurity-doped polycrystalline silicon.
4. The method according to claim 3 , wherein a thickness of the impurity-doped amorphous silicon layer is greater than a thickness of the ohmic contact layer.
5. The method according to claim 1 , wherein the etch condition has an etch selectivity ratio of polycrystalline silicon to amorphous silicon within a range of about 0.6 to about 0.8.
6. The method according to claim 1 , wherein the crystallizing an amorphous silicon layer in the active region includes using a laser apparatus.
7. The method according to claim 1 , further comprising forming alignment keys along an edge portion of the substrate.
8. The method according to claim 7 , wherein the alignment keys are formed of the same material and the same layer as the gate electrode.
9. The method according to claim 7 , wherein the crystallizing an amorphous silicon layer in the active region includes using the alignments keys as a reference.
10. A method of fabricating a liquid crystal display device, comprising:
forming a gate electrode and a gate line connected to the gate electrode on a first substrate;
forming a gate insulating layer on the gate electrode and the gate line;
forming an amorphous silicon layer on the gate insulating layer;
crystallizing the amorphous silicon layer in an active region corresponding to the gate electrode to form a polycrystalline silicon layer;
etching the amorphous silicon layer such that an etch rate of amorphous silicon is greater than an etch rate of polycrystalline silicon to form a semiconductor layer of polycrystalline silicon in the active region;
forming source and drain electrodes on the semiconductor layer and a data line connected to the source electrode;
forming a passivation layer on the source electrode, the drain electrode, and the data line;
forming a pixel electrode on the passivation layer;
forming a black matrix on a second substrate;
forming a color filter layer on the black matrix;
forming a common electrode on the color filter layer;
attaching the first substrate and the second substrate such that the pixel electrode faces the common electrode; and
forming a liquid crystal layer between the pixel electrode and the common electrode.
11. The method according to claim 10 , wherein the forming an amorphous silicon layer includes forming an intrinsic amorphous silicon layer on the gate insulating layer and forming an impurity-doped amorphous silicon layer on the intrinsic amorphous silicon layer.
12. The method according to claim 11 , wherein the semiconductor layer includes an active layer of intrinsic polycrystalline silicon and an ohmic contact layer of impurity-doped polycrystalline silicon.
13. The method according to claim 12 , wherein a thickness of the impurity-doped amorphous silicon layer is greater than a thickness of the ohmic contact layer.
14. The method according to claim 10 , wherein the etch condition has an etch selectivity ratio of polycrystalline silicon to amorphous silicon within a range of about 0.6 to about 0.8.
15. The method according to claim 10 , wherein the crystallizing an amorphous silicon layer in the active region includes using a laser apparatus.
16. The method according to claim 10 , further comprising forming alignment keys along an edge portion of the substrate.
17. The method according to claim 16 , wherein the alignment keys are formed of the same material and the same layer as the gate electrode.
18. The method according to claim 16 , wherein the crystallizing an amorphous silicon layer in the active region includes use the alignment keys as a reference.