Semiconductor integrated circuit device with a metallization structure
View Patent ↗In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.
1. A semiconductor integrated circuit device, comprising:
an insulating film formed over a semiconductor substrate;
a contact hole formed in said insulating film;
a first sputter film formed over the bottom and side walls of said contact hole;
a second sputter film formed over said first sputter film formed over the bottom and side walls of said contact hole; and,
an electroconductive film filling the inside of said contact hole,
wherein said first and second sputter films have a compressive stress, and the compressive stress of said first sputter film is smaller than the compressive stress of said second sputter film.
2. A semiconductor integrated circuit device according to claim 1 , wherein said second sputter film is formed by long throw sputtering.
3. A semiconductor integrated circuit device according to claim 1 , wherein said second sputter film is formed by sputtering using a collimator.
4. A semiconductor integrated circuit device according to claim 1 , wherein said second sputter film is formed by ionized sputtering.
5. A semiconductor integrated circuit device according to claim 1 , wherein the compressive stress of said first sputter film is about 0 to 1 GPa, and the compressive stress of said second sputter film is about 1 to 5 GPa.
6. A semiconductor integrated circuit device, comprising:
a metallization formed over a semiconductor substrate;
an insulating film formed over said metallization;
a contact hole formed in said insulating film;
a first sputter film formed over the bottom and side walls of said contact hole,
a second sputter film formed over said first sputter film formed over the bottom and side walls of said contact hole; and
an electroconductive film filling the inside of said contact hole,
wherein said first and second sputter films have a compressive stress, and the compressive stress of said first sputter film is smaller than the compressive stress of said second sputter film.
7. A semiconductor integrated circuit device according to claim 6 , wherein said metallization is an aluminum metallization and said electroconductive film is a tungsten film.
8. A semiconductor integrated circuit device according to claim 7 , wherein said second sputter film is a film formed by any one of long throw sputtering, sputtering using a collimator and ionized sputtering.
9. A semiconductor integrated circuit device according to claim 6 , wherein said electroconductive film is a copper film.
10. A semiconductor integrated circuit device according to claim 9 , wherein said second sputter film is a film formed by any one of long throw sputtering, sputtering using a collimator and ionized sputtering.
11. A semiconductor integrated circuit device according to claim 6 , wherein said metallization is an aluminum metallization and said electroconductive film is a copper film.
12. A semiconductor integrated circuit device according to claim 11 , wherein said second sputter film is a film formed by any one of long throw sputtering, sputtering using a collimator and ionized sputtering.
13. A semiconductor integrated circuit device according to claim 6 , wherein said first and second sputter films are each a high-melting-point metal film or a film made of a high-melting-point metal compound.
14. A semiconductor integrated circuit device according to claim 6 , wherein said first sputter film is a high-melting-point metal film.
15. A semiconductor integrated circuit device according to claim 6 , wherein said first and second sputter films are each made of Ti, TiN, W, Ta, TaN, TaSiN, TiSiN, TiW or WN.
16. A semiconductor integrated circuit device according to claim 6 , wherein the compressive stress of said first sputter film is about 0 to 1 GPa, and the compressive stress of said second sputter film is about 1 to 5 GPa.