LCD with bent split pixel electrodes with transistor for each partition
View Patent ↗A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and having an intersecting portion intersecting the first signal line and a curved portion connected to the intersecting portion; a first thin film transistor connected to the first and the second signal lines; and a pixel electrode that are connected to the first thin film transistor, includes first and second partitions, and are curved along the curved portion of the second signal line.
1. A thin film transistor array panel comprising:
a substrate;
a first signal line formed on the substrate;
a second signal line formed on the substrate and crossing the first signal line;
a first thin film transistor connected to the first and the second signal lines; and
a pixel electrode connected to the first thin film transistor, the pixel electrode including first and second partitions,
a second thin film transistor connected to the second partition of the pixel electrode, wherein the first thin film transistor is connected to the first partition of the pixel electrode; and
wherein the first partition includes a first edge portion at a first non-zero angle with respect to the fast signal line and a second edge portion at a second different non-zero angle with respect to the first signal line, and wherein the second partition includes a first edge portion adjacent to and physically separated from the first edge portion of the first partition.
2. The thin film transistor array panel of claim 1 , wherein the second signal line includes a pair of rectilinear portions connected to each other and making an angle of about 45 degrees with the first signal line.
3. The thin film transistor array panel of claim 1 , wherein the first and the second partitions of the pixel electrode are disposed opposite each other with respect to the second signal line and the first and the second thin film transistors are disposed opposite each other with respect to the second signal line.
4. The thin film transistor army panel of claim 3 , further comprising a connection connecting the first partition of the pixel electrode and the second partition of the pixel electrode.
5. The thin film transistor array panel of claim 4 , wherein the second signal line includes a first portion at a first non-zero angle to the first signal line and a second portion at a second different non-zero angle to the first signal line, and wherein the connection crosses an intersection region of the second signal line where the first portion and the second portion intersect.
6. The thin film transistor array panel of claim 5 , wherein the connection comprises the same layer as the pixel electrode.
7. The thin film transistor array panel of claim 4 , wherein the second signal line further comprises a crossing portion positioned crossing the first signal line, and wherein the connection is disposed near the crossing portion of the second signal line and comprises the same layer as the pixel electrode.
8. The thin film transistor array panel of claim 1 , wherein at least one edge of the pixel electrode overlaps the second signal line.
9. The thin film transistor array panel of claim 1 , wherein the first edge of the first partition of the pixel electrode and the first edge portion of the second partition of the pixel electrode are physically separated by a gap therebetween, and the gap extends parallel to an associated portion of the second signal line.
10. The thin film transistor array panel of claim 9 , wherein the gap overlaps the associated portion of the second signal line.
11. The thin film transistor array panel of claim 1 , further comprising a third signal line separated from the first and the second signal lines and having a portion overlapping at least one of the pixel electrode and a portion of the first thin film transistor that is connected to the pixel electrode.
12. The thin film transistor array panel of claim 11 , wherein the third signal line further comprises a branch disposed near at least one edge of the first or the second partition of the pixel electrode.
13. The thin film transistor array panel of claim 12 , wherein the at least one edge of the first or the second partition of the pixel electrode overlaps the branch of the third signal line.
14. The thin film transistor array panel of claim 12 , wherein the first edge portion of the first partition and the first edge portion of the second partition of the pixel electrode are physically separated by a gap therebetween, and the gap extends parallel to an associated portion of the second signal line.
15. The thin film transistor array panel of claim 14 , wherein the gap overlaps the branch of the third signal line.
16. The thin film transistor array panel of claim 15 , further comprising a connection connecting the first partition and the second partition of the pixel electrode and wherein the branch is spaced apart from the connection.
17. The thin film transistor array panel of claim 12 , wherein the pixel electrode and the second signal line are separated by a gap therebetween, and wherein the gap extends parallel to the second signal line.
18. The thin film transistor array panel of claim 17 , wherein the branch of the third signal line is disposed between the pixel electrode and the second signal line and overlaps an edge of the pixel electrode.
19. A thin film transistor array panel comprising:
a substrate;
a gate line formed on the substrate and including a gate electrode;
a gate insulating layer formed on the gate line;
a semiconductor layer formed on the gate insulating layer;
a data line having a crossing portion crossing the gate line and including a source electrode formed on the semiconductor layer at least in part;
a first drain electrode formed on semiconductor layer at least in part and located opposite the source electrode;
a passivation layer formed on the semiconductor layer;
a pixel electrode connected to the first drain electrode, wherein the pixel electrode includes first and second partitions, wherein the first partition includes a first edge portion at a first non-zero angle with respect to the gate line and a second edge portion at a second different non-zero angle with respect to the gate line, and wherein the second partition includes a first edge portion adjacent to and physically separated from the first edge portion of the first partition; and
a second drain electrode connected to the second partition of the pixel electrode, and wherein the first drain electrode is connected to the first partition of the pixel electrode.
20. The thin film transistor array panel of claim 19 , wherein the data line includes a pair of rectilinear portions connected to each other and making an angle of about 45 degrees with the gate line.
21. The thin film transistor array panel of claim 19 , further comprising a storage electrode line separated from the gate line and the data line, extending substantially parallel to the gate line, and including a storage electrode having an increased area overlapping the first drain electrode.
22. The thin film transistor array panel of claim 19 , wherein the first and the second partitions are disposed opposite each other with respect to the data line and the first and the second drain electrodes are disposed opposite each other with respect to the data line.
23. The thin film transistor array panel of claim 22 , further comprising a storage electrode line separated from the gate line and the data line, extending substantially parallel to the gate line, and including a storage electrode overlapping an edge of at least one of the first and the second partition of the pixel electrode.
24. The thin film transistor array panel of claim 22 , further comprising a connection connecting the first partition and the second partition of the pixel electrode.
25. The thin film transistor array panel of claim 24 , wherein the connection comprises the same layer as the pixel electrode.
26. The thin film transistor array panel of claim 19 , wherein the data line is disposed near an outer edge of the pixel electrode.
27. The thin film transistor array panel of claim 21 , wherein the data line includes a first segment at a first non-zero angle with respect to the gate line and a second segment at a second different non-zero angle with respect to the gate line, and further comprising a color filter disposed under the passivation layer and including a first segment at the first non-zero angle and a second segment at the second non-zero angle.
28. A liquid crystal display comprising:
a first substrate;
a first signal line formed on the first substrate;
a second signal line formed on the first substrate crossing the first signal line;
a first thin film transistor connected to the first and the second signal lines;
a pixel electrode connected to the thin film transistor and includes first and second partitions, wherein the first partition includes a first edge portion at a first non-zero angle with respect to the first signal line and a second edge portion at a second different non-zero angle with respect to the first signal line, and wherein the second partition includes a first edge portion adjacent to and physically separated from the first edge portion of the first partition;
a second thin film transistor connected to the second partition of the pixel electrode, wherein the first thin film transistor is connected to the first partition of the pixel electrode;
a second substrate facing the first substrate;
a common electrode formed on the second substrate;
a liquid crystal layer interposed between the first substrate and the second substrate; and
a domain definition member dividing the liquid crystal layer into a plurality of domains, each domain having two primary edges parallel to associated portions of the second signal line.
29. The liquid crystal display of claim 28 , further comprising a third signal line separated from the first and the second signal lines, overlapping the pixel electrode to form a storage capacitor, and including a branch extending parallel to the second signal line.
30. The liquid crystal display of claim 28 , wherein the domain definition member comprises a protrusion disposed on the common electrode.
31. The liquid crystal display of claim 28 , wherein the domain definition member comprises a cutout formed at the common electrode or the pixel electrode.