Clock control circuit and method
View Patent ↗A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 11 1 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 11 2 corresponding to the position on the forward route 11 1 . The timing difference between these clocks is averaged to output an averaged timing difference.
1. A clock controlling circuit comprising:
a timing averaging circuit provided with a frequency dividing function for frequency dividing first and second clocks, including the first clock from a first position on a forward route of a clock propagation path fed with input clocks at one end and direction-reversing the input clocks and the second clock from a second position corresponding to said first position to generate frequency divided multi-phase clocks of plural different phases,
said timing averaging circuit outputting a signal of a delay time corresponding to a time equally dividing a timing difference between frequency divided clocks having a corresponding phase among clock signals obtained on frequency division of said two clocks; and
a synthesis circuit for synthesizing plural outputs of said timing averaging circuit into one signal and for outputting said one signal.
2. The clock controlling circuit as defined in claim 1 wherein a delay time between said first position and the direction-reversing point of said clock propagation path is equal to a delay time between said direction-reversing point of said clock propagation path and said second position, and
wherein a plurality of said timing averaging circuits having the frequency dividing function are arranged along a path between a clock input end and a direction-reversing point of said clock propagation path.