Input circuit with hysteresis
View Patent ↗An input circuit has hysteresis to mitigate the effects of input noise. The input circuit receives an analog input signal and determines whether the unregulated analog input signal is a high or a low voltage. The input circuit outputs a regulated low voltage (i.e., “0”) for a low input signal, and outputs a regulated high voltage (i.e., “1”) for a high input signal. The low-to-high transition occurs at a higher voltage than a high-to-low transition, which mitigates noise on the input signal. Furthermore, the comparator includes a feedback path from an output of the comparator to an input of the comparator. The feedback path causes some delay in any output voltage transition (i.e. high-to-low output transition or low-to-high transition), which further enhances the hysteresis effect and improves noise immunity. An embodiment of the circuit interfaces with high voltage (e.g., 5V) input signals and outputs low voltage (e.g., 1.2V) output signals. In other words, the input circuit also provides a voltage transition while detecting the low-to-high and high-to-low transitions.
1. A comparator with hysteresis, comprising:
an input node to receive an input voltage;
first and second transistors configured to provide a first output voltage transition in response to the input voltage exceeding a first threshold voltage and to provide a second output voltage transition in response to the input voltage going below a second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage; and
an inverter coupled between a gate of the first transistor and a gate of the second transistor, wherein the gate of the first transistor is coupled to the input node; and
a feedback coupled between the gate of the second transistor and an output node to delay the first or second output voltage transition at the output node.
2. The comparator of claim 1 , wherein the first and second transistors are MOSFET transistors.
3. The comparator of claim 1 , wherein the first output voltage transition includes a transition from a low output voltage to a high output voltage, and the second output voltage transition includes a transition from a high output voltage to a low output voltage.
4. The comparator of claim 1 , wherein the first transistor is scaled in size relative to the second transistor.
5. The comparator of claim 1 , wherein the first transistor has the first threshold voltage.
6. The comparator of claim 1 , further comprising at least one protection transistor to limit a bias voltage received by at least one of the first and second transistors.
7. The comparator of claim 1 , wherein a buffer stage is coupled to the output node.
8. The comparator of claim 1 , further comprising at least one protection transistor coupled between the input node and the first and second transistors to limit a voltage or a current received at the gates of the first and second transistors.
9. The comparator of claim 1 , further comprising an electrostatic discharge protection stage coupled between the input node and the first and second transistors.
10. The comparator of claim 1 , wherein the input voltage temporarily conflicts with a voltage at the output node in response to a voltage transition of the input voltage, thereby facilitating delay of the first or second output voltage transition.
11. The comparator of claim 1 , wherein in response to an input voltage transition from a low input voltage to a high input voltage at the input node the first transistor is activated to connect a supply voltage to the output node and the second transistor is de-activated by an output of the inverter, and wherein the supply voltage temporarily conflicts with a pre-existing voltage at the gate of the second transistor due to the feedback.
12. The comparator of claim 1 , wherein in response to an input voltage transition from a high input voltage to a low input voltage at the input node the first transistor is de activated and the second transistor is activated by an output of the inverter to connect a supply voltage to the output node, and wherein the supply voltage temporarily conflicts with a pre-existing voltage at the gate of the second transistor due to the feedback.
13. An apparatus, comprising:
a first switching means for connecting an output node to a first supply voltage based on a first state of an input signal;
a second switching means for connecting the output node to a second supply voltage based on a second state of the input signal;
inverting means coupled between the first switching means and the second switching means, wherein an output of the inverting means is coupled to the output node, and wherein the first or second supply voltage at the output node temporarily conflicts with a pre-existing voltage at the output of the inverting means.
14. The apparatus of claim 13 , wherein the first switching means includes a first MOSFET transistor and the second switching means includes a second MOSFET transistor.
15. The apparatus of claim 13 , wherein the first switching means is scaled in size relative to the second switching means.
16. The apparatus of claim 13 , further comprising protection means to limit a bias voltage received by at least one of the first and second switching means.
17. The apparatus of claim 13 , wherein a buffer stage is coupled to the output node.
18. The apparatus of claim 13 , further comprising protection means coupled to an input of the first and second switching means to limit a voltage or a current received at the input of the first and second switching means.
19. The apparatus of claim 13 , further comprising an electrostatic discharge protection stage coupled to an input of the first and second switching means.
20. The apparatus of claim 13 , wherein the first or second supply voltage at the output node temporarily conflicts with the pre-existing voltage at the output of the inverter in response to a change of state of the input signal.