Power supply system
View Patent ↗A power supply unit includes a plurality of power trains and a control assembly. Each power train includes a power factor correction circuit that receives an AC input and generates a first DC output, and a DC/DC converter circuit that receives the first DC output and generates a second regulated DC output. The control assembly is coupled to the power trains and is operative to monitor outputs supplied by the power trains. In response to the power train outputs, the control assembly provides control signals to each power train.
1. A power supply unit (“PSU”) comprising:
a first, second, and third power train, each power train comprising a power factor correction (“PFC”) circuit that receives an AC input and generates a first DC output and a DC/DC converter circuit that receives the first DC output and generates a second regulated DC output; and
a control assembly that is coupled to the first, second, and third power trains, the control assembly being operative to monitor outputs supplied by the first, second, and third power trains and in response thereto being operative to provide control signals to each of the first, second, and third power trains.
2. The system according to claim 1 wherein the control assembly comprises:
a plurality of control assembly input circuits, the control assembly input circuits being operative to measure characteristics relating to each of the power trains and operative to generate a measured characteristics output;
a signal processor having a signal path to the control assembly input circuits, the signal processor being operative to receive the measured characteristics output, perform computations wherein the measured characteristics output is used in the computations, and generate a signal processor output; and
a plurality of control assembly output circuits, the control assembly output circuits being operative to generate error signals based on the signal processor output.
3. The system according to claim 2 wherein the signal processor comprises a digital signal processor.
4. The system according to claim 2 wherein each DC/DC converter circuit further comprises a control circuit, the control circuit in response to the error signals generated by the control assembly output circuits being operative to generate control signals to drive switches in the DC/DC converter circuit.
5. The system according to claim 4 wherein the error signals comprise a common error signal and a first, second, and third specific error signal, the common error signal being provided to each control circuit, the first specific error signal being provided to the first power train's control circuit, the second specific error signal being provided to the second power train's control circuit, and the third specific error signal being provided to the third power train's control circuit.
6. The system according to claim 2 wherein the control assembly is operative to generate error signals that cause each power train to supply an equal amount of the total output current supplied by the PSU.
7. The system according to claim 2 wherein the control assembly further comprises a plurality of algorithms that are executed by the signal processor, one of the algorithms being a current balance algorithm, the current balance algorithm being operative to cause the control assembly to generate error signals that cause each power train to supply an equal amount of the total output current supplied by the PSU.
8. The system according to claim 2 wherein the control assembly further comprises a plurality of algorithms that are executed by the signal processor, one of the algorithms being a brown-out/black-out control algorithm, the brown-out/black-out control algorithm being operative to cause the control assembly to generate error signals that allow the PSU to operate at a reduced output current level when the voltage level of the AC input is below a nominal voltage range.
9. The system according to claim 2 wherein the control assembly further comprises a plurality of algorithms that are executed by the signal processor, one of the algorithms being an extended recharge capability control algorithm, the extended recharge capability control algorithm being operative to cause the control assembly to generate error signals that allow the PSU to supply output current beyond a nominal output current rating level if an environmental condition is met.
10. The system according to claim 2 wherein the control assembly further comprises a plurality of algorithms that are executed by the signal processor, one of the algorithms being a voltage loop control algorithm, the voltage loop control algorithm being operative to cause the control assembly to generate error signals that reduces closed loop instability in a rectifier.
11. A control assembly for a power system having a first, second, and third power train, each power train comprising a power factor correction (“PFC”) circuit that receives an AC input and generates a first DC output and a DC/DC converter circuit that receives the first DC output and generates a second regulated DC output, the control assembly being coupled to the first, second, and third power trains, the control assembly being operative to monitor outputs supplied by the first, second, and third power trains and in response thereto being operative to provide control signals to each of the first, second, and third power trains, the control assembly comprising:
a plurality of control assembly input circuits, the control assembly input circuits being operative to measure characteristics relating to each of the power trains and operative to generate a measured characteristics output;
a signal processor having a signal path to the control assembly input circuits, the signal processor being operative to receive the measured characteristics output, perform computations wherein the measured characteristics output is used in the computations, and generate a signal processor output; and
a plurality of control assembly output circuits, the control assembly output circuits being operative to generate error signals based on the signal processor output.
12. The control assembly according to claim 11 wherein the signal processor comprises a digital signal processor.
13. The control assembly according to claim 11 wherein each DC/DC converter circuit further comprises a control circuit, the control circuit in response to the error signals generated by the control assembly output circuits being operative to generate control signals to drive switches in the DC/DC converter circuit.
14. The control assembly according to claim 13 wherein the error signals comprise a common error signal and a first, second, and third specific error signal, the common error signal being provided to each control circuit, the first specific error signal being provided to the first power train's control circuit, the second specific error signal being provided to the second power train's control circuit, and the third specific error signal being provided to the third power train's control circuit.
15. The control assembly according to claim 11 wherein the control assembly is operative to generate error signals that cause each power train to supply an equal share of the total output current supplied by the power system.
16. The control assembly according to claim 11 further comprising a plurality of algorithms that are executed by the signal processor, one of the algorithms being a current balance algorithm, the current balance algorithm being operative to cause the control assembly to generate error signals that cause each power train to supply an equal share of the total output current supplied by the power system.
17. The control assembly according to claim 11 further comprising a plurality of algorithms that are executed by the signal processor, one of the algorithms being a brown-out/black-out control algorithm, the brown-out/black-out control algorithm being operative to cause the control assembly to generate error signals that allow the power system to operate at a reduced output current level when the voltage level of the AC input is below a nominal voltage range.
18. The control assembly according to claim 11 further comprising a plurality of algorithms that are executed by the signal processor, one of the algorithms being an extended recharge capability control algorithm, the extended recharge capability control algorithm being operative to cause the control assembly to generate error signals that allow the power system to supply output current beyond a nominal output current rating level if an environmental condition is met.
19. The control assembly according to claim 11 further comprising a plurality of algorithms that are executed by the signal processor, one of the algorithms being a voltage loop control algorithm, the voltage loop control algorithm being operative to cause the control assembly to generate error signals that reduces closed loop instability in a rectifier.
20. A control assembly for a power system having a power train, the power train comprising a DC/DC converter circuit that receives a first DC voltage and generates a second regulated DC output, the control assembly being coupled to the power train, the control assembly being operative to monitor outputs supplied by the power train and in response thereto being operative to provide control signals to the power train, the control assembly comprising:
a plurality of control assembly input circuits, the control assembly input circuits being operative to measure characteristics relating to the power train and operative to generate a measured characteristics output;
a signal processor having a signal path to the control assembly input circuits, the signal processor being operative to receive the measured characteristics output, perform computations wherein the measured characteristics output is used in the computations, and generate a signal processor output; and
a plurality of control assembly output circuits, the control assembly output circuits being operative to generate error signals based on the signal processor output.
21. The control assembly according to claim 20 wherein the signal processor comprises a digital signal processor.
22. The control assembly according to claim 20 wherein the DC/DC converter circuit further comprises a control circuit, the control circuit in response to the error signals generated by the control assembly output circuits being operative to generate control signals to drive switches in the DC/DC converter circuit.
23. The control assembly according to claim 20 further comprising a plurality of algorithms that are executed by the signal processor, one of the algorithms being a brown-out/black-out control algorithm, the brown-out/black-out control algorithm being operative to cause the control assembly to generate error signals that allow the power system to operate at a reduced output current level when the voltage level of the AC input is below a nominal voltage range.
24. The control assembly according to claim 20 further comprising a plurality of algorithms that are executed by the signal processor, one of the algorithms being an extended recharge capability control algorithm, the extended recharge capability control algorithm being operative to cause the control assembly to generate error signals that allow the power system to supply output current beyond a nominal output current rating level if an environmental condition is met.
25. The control assembly according to claim 20 further comprising a plurality of algorithms that are executed by the signal processor, one of the algorithms being a voltage loop control algorithm, the voltage loop control algorithm being operative to cause the control assembly to generate error signals that reduces closed loop instability in a rectifier.