Driving scheme for cholesteric liquid crystal display
View Patent ↗A drive scheme is described for a display capable of gray scale. Multiple two-level pulses are used in conjunction with dynamic relaxation techniques to write pixels ON or OFF and to adjust the gray level of pixels. Only two voltage levels are used, a maximum level U, and a minimum level 0. This reduces the complexity of the electronics so that the only one voltage generator is needed for the display.
1. A method of forming a gray scale of multiple gray levels on a bistable liquid crystal material having incremental reflectance properties disposed between a first and second plurality of electrodes, an intersection of the first and second plurality of electrodes forming a pixel having a pixel pulse voltage, the addressing method comprising:
applying a first number of pulses, wherein a voltage level of said pulses is at either predetermined levels of 0 volts or U volts only, to the first plurality of electrodes; and
applying a second number of pulses, wherein a voltage level of said pulses is at either predetermined levels of 0 volts or U volts only, to the second plurality of electrodes, each of the pulses having a different frequency, wherein each pixel pulse voltage has a root mean square value of U volts.
2. The method of claim 1 , wherein the first number and second number of pulses are the same.
3. The method of claim 1 , wherein at least two of the number of pulses have the same frequency.
4. The method of claim 2 , wherein at least two of the number of pulses have the same frequency.
5. The method of claim 1 , wherein the first plurality and second plurality of pulses are applied while the liquid crystal material is relaxing from a homeotropic state to a transient planar state.
6. A method of forming a gray scale of multiple gray levels on a bistable liquid crystal material having incremental reflectance properties disposed between a first and second plurality of electrodes, an intersection of the first and second plurality of electrodes forming a pixel, the addressing method comprising:
applying a number of pulses, wherein a voltage level of said pulses is at either predetermined levels of 0 volts or U volts only, to the first plurality of electrodes; and
applying the same number of pulses, wherein a voltage level of said pulses is at either predetermined levels of 0 volts or U volts only, to the second plurality of electrodes, wherein at least two of the number of pulses have the same frequency.
7. The method of claim 6 , wherein each pulse has a root mean square value of U.
8. A method of forming a gray scale on a bistable liquid crystal material having incremental reflectance properties disposed between a first and second plurality of electrodes, an intersection of the first and second plurality of electrodes forming a pixel, the method comprising:
applying a first number of pulses, wherein a voltage level of said pulses is at either predetermined levels of 0 volts or U volts only, to the first plurality of electrodes;
applying a second number of pulses, wherein a voltage level of said pulses is at either predetermined levels of 0 volts or U volts only, to the second plurality of electrodes, wherein each pulse has the same voltage level.
9. The method of claim 8 , wherein the first number and second number of pulses are the same.
10. The method of claim 8 , wherein at least two of the number of pulses have the same frequency.
11. A method of forming a gray scale of multiple gray levels on a bistable liquid crystal material having incremental reflectance properties disposed between a first and second plurality of electrodes, an intersection of the first and second plurality of electrodes forming a pixel, the addressing method comprising:
a preparation phase;
a pre-selection phase;
a selection phase accomplished by:
addressing one group of pixels, associated with an intersection of one first patterned conductor and all second patterned conductors, for a selection time, Ts, where the selection time, Ts, is divided into sub-selections n, where n must be at least 1, by apply a number of pulses wherein a voltage waveform for any pixel of the one group of pixels within said sub-selection has a voltage level of either 0 volts or a predetermined RMS value of U volts and wherein there are as many as 2 n different combinations of pulses having a voltage level of 0 or U volts during the entire selection time Ts;
addressing a second group of pixels associated with an intersection of a different first patterned conductor and all second patterned conductors can be addressed for a second selection time Ts;
repeating said addressing until all groups of pixels are addressed;
a post-selection phase; and
an evolution phase.
12. The method of claim 11 , wherein said sub-selections are the same.
13. The method of claim 11 , wherein at least two of said sub-selections are the same.
14. The method of claim 11 , wherein said sub-selections are different.