Dynamic register with IDDQ testing capability
View Patent ↗The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate. The method includes the operations of driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.
1. A method for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage, the circuit including a transmission gate having an input terminal and an output terminal, the transmission gate operating in response to a clock signal, the node being coupled to the output terminal of the transmission gate, wherein when the transmission gate is open, the input signal at the input terminal of the transmission gate drives the node, the method comprising:
when the transmission gate is closed, pulling the node to a fixed voltage using a control circuit, the control circuit including a logic gate and a transistor, the logic gate having an output and being responsive to the clock signal and a test signal, the transistor having a gate terminal coupled to the output of the logic gate, the control circuit being coupled to the node via the transistor.
2. The method of claim 1 wherein a substantial amount of power supply current is prevented from dissipating in the circuit while the transmission gate is closed.
3. The method of claim 1 wherein the clock signal has a first steady state and a second steady state and wherein during the first steady state of the clock signal, the transmission gate is open and wherein during the second steady state of the clock signal, the transmission gate is closed.
4. The method of claim 1 wherein the test signal indicates whether the circuit is undergoing an IDDQ test.
5. The method of claim 4 wherein when the circuit is undergoing an IDDQ test and the transmission gate is opened in response to the clock signal, the transistor in the control circuit is turned off at substantially the same time as the transmission gate is opened, so that the control circuit does not affect the voltage at the node.
6. The method of claim 1 wherein the logic gate is a NAND gate.
7. The method of claim 1 wherein the logic gate is an AND gate.
8. The method of claim 1 wherein the circuit includes an inverter disposed in series with the transmission gate, the node being located between the transmission gate and the inverter.
9. The method of claim 1 wherein the transmission gate is of CMOS type.
10. The method of claim 1 wherein the operation of pulling the node to a fixed voltage comprises turning on the transistor in the control circuit, at substantially the same time as the transmission gate is closed, so as to pull the voltage of the node to a fixed voltage via the transistor.
11. The method of claim 1 wherein the circuit is a dynamic register.
12. The method of claim 11 wherein the dynamic register is included in a gigabit transceiver chip.
13. A system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage, the circuit including a transmission gate having an input terminal and an output terminal, the node being coupled to the output terminal of the transmission gate, wherein when the transmission gate is open, the input signal at the input terminal of he transmission gate drives the node, the system comprising:
a control circuit coupled to the circuit at the node, the control circuit not controlling the voltage at the node en the transmission gate is open and pulling the node to a fixed voltage when the transmission gate is closed.
14. The system of claim 13 wherein a substantial amount of power supply current is prevented am dissipating in the circuit while the transmission gate is closed.
15. The system of claim 13 wherein the transmission gate operates in response to a clock signal.
16. The system of claim 15 wherein the clock signal has a first steady state and a second steady state and wherein during the first steady state of the clock signal, the transmission gate is open and wherein during the second steady state of the clock signal, the transmission gate is closed.
17. The system of claim 15 wherein the control circuit includes a logic gate and a transistor, the logic gate having an output and being responsive to the clock signal and a test signal, the transistor having a gate terminal coupled to the output of the logic gate, the control circuit being coupled to the node via the transistor.
18. The system of claim 17 wherein the test signal indicates whether the circuit is undergoing IDDQ test.
19. The system of claim 18 wherein when the circuit is undergoing an IDDQ test and the transmission gate is opened in response to the clock signal, the control circuit turns off the transistor at substantially the same time as the transmission gate is opened so that the control circuit does not control the voltage at the node when the transmission gate is open.
20. The system of claim 17 wherein the logic gate is a NAND gate.
21. The system of claim 17 wherein the logic gate is an AND gate.
22. The system of claim 17 wherein the control circuit turns on the transistor at substantially the same time as the transmission gate is closed in response to the clock signal, to pull the voltage of the node to a fixed voltage via the transistor.
23. The system of claim 13 wherein the circuit includes an inverter disposed in series with the transmission gate, the node being located between the transmission gate and the inverter.
24. The system of claim 13 wherein the transmission gate is of CMOS type.
25. The system of claim 13 wherein the circuit is a dynamic register.
26. The system of claim 25 wherein the dynamic register is included in a gigabit transceiver chip.