Radiation-hardened silicon-on-insulator CMOS device, and method of making the same

1. A silicon-on-insulator metal oxide semiconductor device comprising:

an ultrathin silicon layer on a sapphire substrate;

at least one P-channel MOS transistor formed in the ultrathin silicon layer;

N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire substrate is at least 10 times greater than peak impurity concentration in the ultrathin silicon layer.

2. The device of claim 1 ,

wherein the N-type impurity implanted within the sapphire substrate has a peak concentration disposed at least 0.05 microns from a silicon-sapphire back interface.

3. The device of claim 1 ,

wherein the peak N-type impurity concentration within the sapphire substrate is approximately 1.0×10 19 ions/cm 2 .

4. A silicon-on-insulator metal oxide semiconductor device comprising:

an ultrathin silicon layer on a sapphire substrate;

at least one P-channel MOS transistor formed in the ultrathin silicon layer;

N-type impurity implanted within the sapphire substrate such that peak N-type impurity concentration within the sapphire substrate is disposed at least 0.05 microns from a silicon-sapphire back interface.

5. The device of claim 4 ,

wherein the N-type impurity implanted within the sapphire substrate has a peak impurity concentration disposed at least 0.10 microns from a silicon-sapphire back interface.

6. The device of claim 4 ,

wherein the peak N-type impurity concentration within the sapphire substrate is approximately 1.0×10 19 ions/cm 2 .

7. A silicon-on-insulator metal oxide semiconductor device comprising:

an ultrathin silicon layer on a sapphire substrate;

at least one P-channel MOS transistor formed in the ultrathin silicon layer;

N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration of approximately 1.0×10 19 ions/cm 2 in the sapphire layer, which is at least 10 times greater than peak impurity concentration in the ultrathin silicon layer and which is disposed at least 0.05 microns from a silicon-sapphire back interface.

8. A silicon-on-insulator metal oxide semiconductor device comprising:

an ultrathin silicon layer on a sapphire substrate;

at least one P-channel MOS transistor formed in the ultrathin silicon layer;

wherein the ultrathin silicon layer is characterized by a retrograde N-type dopant concentration profile in the P-channel region;

wherein the sapphire substrate is characterized by a retrograde N-type dopant concentration in the sapphire substrate opposite the P-channel region; and

wherein peak N-type dopant concentration is at least 10 times higher in the sapphire substrate than peak N-type dopant concentration in the P-channel region.

9. The device of claim 8 further including:

an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;

wherein the retrograde N-type dopant concentration profile in the P-channel region the retrograde N-type dopant concentration profile in the sapphire substrate opposite the P-channel region together form a retrograde N-type dopant concentration profile across the P-channel region, the interface region and the sapphire substrate opposite the P-channel region.

10. The device of claim 8 ,

an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;

wherein the retrograde N-type dopant concentration in the sapphire substrate increases with increasing distance from the interface region up to a peak concentration region and trails off after the peak concentration region, with increasing distance from the interface region.

11. A silicon-on-insulator metal oxide semiconductor device comprising:

an ultrathin silicon layer on a sapphire substrate;

at least one P-channel MOS transistor formed in the ultrathin silicon layer;

wherein the ultrathin silicon layer is characterized by a retrograde N-type dopant concentration profile in the P-channel region;

wherein the sapphire substrate is characterized by a retrograde N-type dopant concentration in the sapphire substrate opposite the P-channel region; and

wherein peak N-type dopant concentration is in the sapphire substrate and is disposed at least 0.05 microns from a silicon-sapphire back interface.

12. The device of claim 11 further including:

an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;

wherein the retrograde N-type dopant concentration profile in the P-channel region the retrograde N-type dopant concentration profile in the sapphire substrate opposite the P-channel region together form a retrograde N-type dopant concentration profile across the P-channel region, the interface region and the sapphire substrate opposite the P-channel region.

13. The device of claim 11 ,

an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;

wherein the retrograde N-type dopant concentration in the sapphire substrate increases with increasing distance from the interface region up to a peak concentration region and trails off after the peak concentration region, with increasing distance from the interface region.

14. The device of claim 1 further including:

an N-type threshold voltage setting implant in the P-channel region.

15. The device of claim 1 further including:

an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;

wherein the retrograde N-type dopant concentration profile in the P-channel region is substantially continuous with the retrograde N-type dopant concentration profile in the sapphire substrate opposite the P-channel region so as to form a substantially continuous N-type dopant concentration profile across the P-channel region, the interface region and the sapphire substrate opposite the P-channel region;

wherein the retrograde N-type dopant concentration in the sapphire substrate increases with increasing distance from the interface region up to a peak concentration region, which is at prescribed distance from the interface region, and trails off after the peak concentration region, with increasing distance from the interface region; and

wherein the prescribed distance is selected to be far enough from the interface region that radiation-induced charge that may become trapped does not produce an inversion region near the interface region.

16. A device according to claim 1 or 4 ,

wherein the N-channel dopant is selected from the group consisting of phosphorous, arsenic and antimony.

17. A device according to claim 1 or 4 further including:

an N-channel device interconnected with the P-channel device to from a CMOS device.

18. The device of claim 1 or 4 ,

wherein respective source and drain regions of the P-channel device extend to a silicon-sapphire interface.