Data-signal-recovery circuit, data-signal-characterizing circuit, and related integrated circuits, systems, and methods

1. A data signal recovery circuit in a receiver, comprising:

a data signal conditioner configured to alter a parameter of an input data signal;

a first sampling flip-flop configured to receive the conditioned data signal and, in response to a sample clock signal, configured to generate a recovered digital signal having a first level if the conditioned data signal is above a first threshold provided by the first threshold circuit and having a second level if the conditioned data signal is below the first threshold;

a second sampling flip-flop comprising a second threshold circuit, the second sampling flip-flop being configured to receive the conditioned data signal, and, in response to the sample clock signal, being configured to generate a test digital signal having a third level if the conditioned data signal is above a second threshold provided by the second threshold circuit and having a fourth level if the conditioned data signal is below the second threshold; and

a controller coupled to the data signal conditioner and to the first and second sampling flip-flops and configured to monitor the parameter of the data signal and to control the altering of the parameter in response to the recovered digital signal and test digital signal;

wherein the first threshold circuit is integrated into and forms a portion of the first sampling flip-flop and the second threshold circuit is integrated into and forms a portion of the second sampling flip-flop such that delays and phase shifts occurring between the first threshold circuit and the first flip-flop, and between the second threshold circuit and the second flip-flop, are minimized, and such that the data signal recovery signal circuit can operate in the receiver at high weed with little or no delay, little or no phase shifts, and low amplitude distortion.

2. The data signal recovery circuit of claim 1 , wherein the controller is further operable to sweep a phase of the sample clock signal relative to the data clock through a first range and to sweep the second threshold through a second range.

3. The data signal recovery circuit of claim 1 , wherein the data signal conditioner comprises an equalizer.

4. The data signal recovery circuit of claim 1 , wherein the data signal conditioner comprises a pre-emphasis circuit.

5. The data signal recovery circuit of claim 1 , wherein:

the data-signal conditioner is disposed on a first integrated circuit; and

the first and second sampling flip-flops and the control circuit are disposed on one or more integrated circuits that are separate from the first integrated circuit.

6. The data signal recovery circuit of claim 1 , wherein the controller is operably coupled to the sampler and is operable to sweep a phase of an intermediate clock signal relative to a data clock signal through a first range, to generate the sample clock signal in response to respective predetermined edges of the intermediate clock signal, to detect an error when the test digital signal has a predetermined relationship to the recovered digital signal, and to identify a boundary of an eye of the input data signal in response to an error-detection rate.

7. The data signal recovery circuit of claim 1 , further comprising a phase shifter coupled between the first or second sampling flip-flops and the controller and configured to generate a predetermined phase shift in the sample clock signal relative to the data clock signal.

8. The data signal recovery circuit of claim 1 , further comprising a clock recovery circuit operably coupled to the phase shifter and configured to recover the data clock signal from the input data signal.

9. The data signal recovery circuit of claim 1 , wherein the third level equals the first level and the fourth level equals the second level.

10. The data signal recovery circuit of claim 1 , wherein the sample clock signal has a random period.

11. The data signal recovery circuit of claim 1 , wherein the sample clock signal has a pseudo-random period.

12. The data signal recovery circuit of claim 1 , wherein the sample clock signal has a substantially constant first period and an intermediate clock has a substantially constant second period that is different than the first period.

13. The data signal recovery circuit of claim 1 , further comprising a synchronizer coupled to the first and second sampling flip-flops and operable to synchronize the recovered digital signal and the test digital signal to the data clock; and

a comparator coupled to the synchronizer and to the controller and operable to compare the synchronized recovered and test digital signals.

14. The data signal recovery circuit of claim 1 , wherein the controller is further configured to adjust the phase of the sample clock signal and the first or second thresholds such that a sampling point defined by a sampling edge of the sample clock signal and the first threshold is within an eye of the input data signal.