Smooth metal semiconductor surface and method for making the same
View Patent ↗A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the metal layer may be substantially absent of any material laterally adjacent to the metal layer during polishing. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained. As such, the method may include reducing the mean surface roughness of a metal layer. For example, the method may include reducing the mean surface roughness of a metal layer by at least a factor of ten.
1. A magnetic random access memory device comprising a digit line with a mean surface roughness of less than approximately 10 angstroms, wherein the digit line comprises tungsten nitride.
2. The magnetic random access memory device of claim 1 , wherein said mean surface roughness is less than approximately 3.0 angstroms.
3. The magnetic random access memory device of claim 1 , wherein the digit line comprises a thickness between approximately 1000 angstroms and approximately 3000 angstroms.
4. The magnetic random access memory device of claim 1 , wherein said mean surface roughness is less than approximately 2.0 angstroms.
5. A magnetic random access memory device comprising a metal layer with a mean surface roughness of less than approximately 10 angstroms, wherein the metal layer comprises titanium nitride.
6. The magnetic random access memory device of claim 1 , wherein said mean surface roughness is less than approximately 3.0 angstroms.
7. The magnetic random access memory device of claim 1 , wherein said metal layer comprises a digit line of the magnetic random access memory device.
8. The magnetic random access memory device of claim 5 , wherein said metal layer is a layer within a magnetic tunneling junction of the magnetic random access memory device.
9. The magnetic random access memory device of claim 5 , wherein said metal layer is arranged within a gate structure of the magnetic random access memory device.
10. The magnetic random access memory device of claim 5 , wherein said metal layer is arranged within an interconnect line of the magnetic random access memory device.
11. The magnetic random access memory device of claim 5 , wherein the metal layer comprises a thickness between approximately 300 angstroms and approximately 3000 angstroms.
12. The magnetic random access memory device of claim 5 , wherein said mean surface roughness is less than approximately 2.0 angstroms.
13. The magnetic random access memory device of claim 5 , wherein the metal layer is arranged underneath a tunneling layer of a magnetic tunneling junction within the magnetic random access memory device.
14. A semiconductor topography comprising a metal nitride layer with a thickness between approximately 300 angstroms and approximately 3000 angstroms and a mean surface roughness of less than approximately 10 angstroms, wherein said metal nitride layer is arranged within a gate structure of the semiconductor topography.
15. The semiconductor topography of claim 14 , wherein said mean surface roughness is less than approximately 3.0 angstroms.
16. The semiconductor topography of claim 14 , wherein the metal nitride layer comprises tungsten nitride.
17. The semiconductor topography of claim 14 , wherein the metal nitride layer comprises titanium nitride.
18. The semiconductor topography of claim 14 , wherein said mean surface roughness is less than approximately 2.0 angstroms.