High frequency divider state correction circuit
View Patent ↗The present invention provides for state correction. A first value in a state circuit is received from a flip flop. The received value is transmitted to a second flip flop. The received value within the second flip flop is altered if an error condition arises. The received value is transmitted to a third flip flop. In one aspect, the received value transmitted to the third flip flop comprises an unaltered received value. In another aspect, the received value transmitted to the third flip flop comprises transmitting an altered received value. This allows for an incorrect state within the state machine to change to a correct state after a few clock pulses.
1. A frequency divider state circuit, comprising:
a first flip flop coupled to receive a feedback signal and a clock signal, and configured to produce a first output signal dependent upon the feedback signal and the clock signal;
a second flip flop coupled to receive the first output signal, the clock signal, and an error signal indicative of an error state, wherein the second flip flop comprises logic coupled to receive the clock signal and the error signal and configured to produce an internal clock signal dependent upon the clock signal and the error signal, and wherein the second flip flop is configured to produce a second output signal dependent upon the first output signal, the clock signal, and the internal clock signal;
a third flip flop coupled to receive the second output signal and the clock signal, and configured to produce a third output signal dependent upon the second output signal and the clock signal; and
wherein the frequency divider state circuit is configured to produce an output signal having a frequency that is less than a frequency of the clock signal.
2. The frequency divider state circuit of claim 1 , wherein the frequency of the output signal of the frequency divider state circuit is substantially the frequency of the clock signal divided by 8.
3. The frequency divider state circuit of claim 1 , wherein at least one of the first, second, and third flip flops is a D type flip flop.
4. The frequency divider state circuit of claim 1 , further comprising:
OR logic coupled to receive the first output signal, a logically inverted version of the second output signal, and the third output signal, and configured to produce the error signal.
5. The frequency divider state circuit of claim 4 , wherein the error signal is a low logic level for at least one specifically defined invalid state.
6. The frequency divider state circuit of claim 1 , wherein the feedback signal is produced by another flip flop of the state divider circuit.
7. The frequency divider state circuit of claim 1 , further comprising:
a fourth flip flop coupled to receive the third output signal and the clock signal, and configured to produce the feedback signal dependent upon the third output signal and the clock signal.
8. The frequency divider state circuit of claim 1 , wherein the first, second, and third flip flops comprise a plurality of latches.
9. The frequency divider state circuit of claim 1 , wherein the frequency divider state circuit is employed in a computer or an electronic data processor.
10. The frequency divider state circuit of claim 4 , further comprising:
a memory element coupled to receive the error signal and configured to produce a time delayed version of the error signal; and
wherein the second flip flop is coupled to receive the first output signal, the clock signal, and the time delayed version of the error signal, and configured to produce a second output signal dependent upon the first output signal, the clock signal, and the time delayed version of the error signal.
11. The frequency divider state circuit of claim 10 , wherein the memory element comprises gate memory.
12. The frequency divider state circuit of claim 1 , wherein the second flip flop comprises exclusive-OR logic coupled to receive the clock signal and the error signal, and configured to produce the internal clock signal dependent upon the clock signal and the error signal.
13. The frequency divider state circuit of claim 12 , wherein the second flip flop comprises:
a first latch coupled to receive the first output signal and the clock signal, and configured to produce an internal signal dependent upon the first output signal and the clock signal; and
a second latch coupled to receive the internal signal and the internal clock signal, and configured to produce the second output signal dependent upon the internal signal and the internal clock signal.
14. A frequency divider state circuit, comprising:
a first flip flop coupled to receive a first feedback signal and a clock signal, and configured to produce a first output signal and an inverted version of the first output signal dependent upon the feedback signal and the clock signal;
a second flip flop coupled to receive the first output signal and the clock signal, and configured to produce a second output signal and an inverted version of the second output signal dependent upon the first output signal and the clock signal;
a correction circuit coupled to receive the inverted versions of the first and second output signals and a second feedback signal, and configured to produce a third output signal dependent upon the inverted versions of the first and second output signals and the second feedback signal;
a third flip flop coupled to receive the third output signal and the clock signal, and configured to produce a fourth output signal, and an inverted version of the fourth output signal as the second feedback signal, dependent upon the third output signal and the clock signal;
a fourth flip flop coupled to receive the fourth output signal and the clock signal, and configured to produce a fifth output signal dependent upon the fourth output signal and the clock signal; and
wherein the frequency divider state circuit is configured to produce an output signal having a frequency that is less than a frequency of the clock signal.
15. The frequency divider state circuit of claim 14 , further comprising selection logic coupled to receive the first, second, fourth, and fifth output signals, and configured to produce an inverted version of either the first output signal, the second output signal, the fourth output signal, or the fifth output signal as the first feedback signal.