Semiconductor device having SiGe channel region
View Patent ↗A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an n − Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.
1. A semiconductor device comprising:
a substrate;
a semiconductor layer provided in a part of the substrate;
a gate insulator film provided on the semiconductor layer;
a gate electrode provided on the gate insulator film; and
n-type source and drain regions provided in regions at both sides of the gate electrode of the semiconductor layer,
wherein the semiconductor layer further includes a first semiconductor layer containing Si and Ge as constituent elements and p-type impurities in a concentration of about at least 1×10 17 atoms·cm −3 ; and
a second semiconductor layer provided in a region directly under the first semiconductor layer, made mainly of Si, and containing p-type impurities.
2. The semiconductor device according to claim 1 , wherein the semiconductor layer further includes a Si layer containing p-type impurities and is sandwiched between the first semiconductor layer and the gate insulator film.
3. The semiconductor device according to claim 2 , wherein a concentration of the p-type impurities contained in the first semiconductor layer is the same as a concentration of the p-type impurities contained in the Si layer.
4. The semiconductor device according to claim 2 , wherein a concentration of the p-type impurities contained in the second semiconductor layer is higher than a concentration of the p-type impurities contained in the first semiconductor layer, and
a concentration of the p-type impurities contained in the first semiconductor layer is the same as a concentration of the p-type impurities contained in the Si layer.
5. The semiconductor device according to claim 1 , further comprising a conductor member for electrically connecting the gate electrode and the second semiconductor layer.
6. The semiconductor device according to claim 1 , wherein at least an uppermost portion of the substrate comprises an insulator.
7. The semiconductor device according to claim 1 , wherein the gate electrode comprises polysilicon or polysilicon germanium containing n-type impurities.
8. The semiconductor device according to claim 1 , wherein the first semiconductor layer is made of SiGe.
9. The semiconductor device according to claim 1 , wherein the first semiconductor layer further contains carbon in a concentration from 0.01% to 2%.
10. The semiconductor device according to claim 1 , further comprising
another semiconductor layer provided on the substrate;
another gate insulator film provided on the other semiconductor layer;
another gate electrode provided on the other gate insulator film; and
p-type source and drain regions provided in regions on both sides of the other gate electrode of the other semiconductor layer,
wherein the other semiconductor layer further includes another first semiconductor layer containing Si and Ge as constituent elements and n-type impurities; and
another second semiconductor layer made of Si and containing n-type impurities is provided in a region under the first semiconductor layer.
11. The semiconductor device according to claim 10 , wherein the other semiconductor layer further includes another Si layer sandwiched between the other first semiconductor layer and the other gate insulator film and containing n-type impurities.
12. The semiconductor device according to claim 1 , wherein a concentration of the p-type impurities contained in a layer of the second semiconductor layer is higher than a concentration of the p-type impurities contained in the first semiconductor layer.
13. The semiconductor device according to claim 1 , wherein the second semiconductor layer includes a layer containing p-type impurities of no less than 1×10 18 cm −3 .
14. The semiconductor device according to claim 1 , wherein the second semiconductor layer includes a first layer and a second layer formed on the first layer, said first layer having a higher concentration of the p-type impurities than the second layer.
15. The semiconductor device according to claim 14 ,
wherein the gate electrode is electrically connected to the first layer.