Clock controlling method and circuit
View Patent ↗A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.
1. A clock control circuit comprising:
a control circuit for producing a control signal for cumulatively adding or cumulatively subtracting to or from a phase relative to a reference clock, by a predetermined unit value of a phase differential for each clock period of said reference clock, said reference clock being an input clock or a clock generated from the input clock; and
a phase adjustment circuit fed with the input clock for generating an output clock having a phase relative to said reference clock, said phase being cumulatively added or cumulatively subtracted by the predetermined unit value of the phase differential based on said control signal; whereby said output clock of a frequency is allowed to be in a non-integer relation with respect to a frequency of said reference clock.
2. A clock control circuit comprising:
a control circuit for generation of a control signal for cumulatively adding or cumulatively subtracting to or from a phase difference of an output clock relative to an input clock by a unit value of the phase difference; and
a phase adjustment circuit fed with said input clock for generating and outputting an output clock having said phase difference prescribed by said control signal.
3. A clock control circuit comprising:
a frequency dividing circuit fed with an input signal to frequency divide the input clock to output a frequency divided clock;
a control circuit for generation of a control signal cumulatively adding or cumulatively subtracting to or from a phase difference relative to said frequency divided clock by a unit value of the phase difference based on the frequency divided clock output from said frequency dividing circuit; and
a phase adjustment circuit fed with said input clock and generating and outputting an output clock having said phase prescribed by said control signal from said control circuit.
4. The clock control circuit as defined in claim 3 wherein
said unit value of the phase difference is variably set by a mode signal input from outside.
5. A clock control method comprising the steps of:
frequency dividing an input clock by a frequency divider receiving the input clock;
generating a control signal, based on the frequency divided clock, for cumulatively adding or cumulatively subtracting by a preset unit value of a phase differential to or from a phase difference relative to the frequency divided clock; and
generating an output clock of the phase difference as set by said control signal.