IP Library › Patent Application 10851697
Patent Application Utility
App. No. 10/851,697 · Confirmation No. 9242

Systems and methods for implementing a rate converting, low-latency, low-power block interleaver

Inventor: Sudhir K. Sharma
Abandoned -- Failure to Respond to an Office Action View Publication ↗
⬇ PDF
 Code Description Pages PDF
2007-07-31 ABN Abandonment 2 View
2007-01-12 CTNF Non-Final Rejection 8 View
2007-01-12 1449 List of References cited by applicant and considered by examiner 1 View
2007-01-12 892 List of references cited by examiner 1 View
2007-01-12 FWCLM Index of Claims 1 View
2007-01-12 BIB Bibliographic Data Sheet 1 View
2007-01-12 SRFW Search information including classification, databases and other search related notes 1 View
2006-12-24 SRNT Examiner's search strategy and results 1 View
2005-02-02 IDS Information Disclosure Statement (IDS) Form (SB08) 4 View
2004-09-01 PEFR Applicant Response to Pre-Exam Formalities Notice 5 View
2004-09-01 OATH Oath or Declaration filed 6 View
2004-07-21 PEFN Pre-Exam Formalities Notice 2 View
2004-05-21 TRNA Transmittal of New Application 1 View
2004-05-21 SPEC Specification 23 View
2004-05-21 CLM Claims 5 View
2004-05-21 ABST Abstract 1 View
2004-05-21 DRW Drawings-only black and white line drawings 11 View
2004-05-21 WFEE Fee Worksheet (SB06) 1 View
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
App. No.
10/851,697
Filed
2004-05-21
Pub. No.
US20040268207A1
Art Unit
2112