Clock controlling method and circuit
View Patent ↗A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.
1. A clock control circuit comprising:
a multi-phase multiplication clock generating circuit receiving an input clock to generate first to nth clocks of respective different phases (termed multi-phase multiplication clocks) obtained by frequency multiplying the input clock;
a switch for selecting two sets each of two neighboring ones of said first to nth clocks output from said multi-phase multiplication clock generating circuit;
a first interpolator receiving the first set of two clocks output from said switch to generate a first signal, a propagation delay of said first signal corresponding to division of timing difference of said first set of two clocks;
a second interpolator receiving the second set of two clocks output from said switch to generate a second signal, a propagation delay of said second signal corresponding to division of timing difference of said second set of two clocks;
a third interpolator receiving said first and second signals of said first and second interpolators to generate a third signal, a propagation delay of said third signal corresponding to division of timing difference of said first and second signals;
a ratio of the internal division of the timing difference of at least one of said first to third interpolators being variably set; and
a control circuit for outputting a switching signal for said switch and a control signal for variably setting the ratio of the internal division of the timing difference of said interpolators.
2. A clock control circuit comprising:
a frequency divider receiving an input clock to generate two sets of clocks of respective different phases obtained on frequency division of said input clock;
a first interpolator receiving the first set of two clocks output from said frequency divider to generate a first signal, a propagation delay of said first signal corresponding to division of timing difference of said first set of two clocks;
a second interpolator receiving the second set of two clocks output from said frequency divider to generate a second signal, a propagation delay of said second signal corresponding to division of timing difference of said second set of two clocks;
a third interpolator receiving first and second signals of said first and second interpolators to generate a third signal, a propagation delay of third signal corresponding to division of timing difference of said first and second signals;
a ratio of internal division of the timing difference of at least one of said first to third interpolators being variably set; and
a control circuit for outputting said switching signal for said switch and a control signal for variably setting the ratio of internal division of the timing difference of said interpolators.