Pulse width modulation based digital incremental encoder
View Patent ↗A digital incremental encoder for generating an output signal indicative of an angular position, a direction of rotation, and a speed of rotation of a shaft. A counter receives a PWM signal indicative of the angular position of the shaft and a clock signal from an angular position sensor, and generates a multi-bit output. A latch latches the multi-bit output, a first bit and a second bit of which are used to generate the output signals that include the first bit. The first bit and the second bit may be XOR'd together to generate an XOR output included in the output signals. A direction of rotation may be derived from a quadrature phase relationship between the first bit and the XOR output. The angular position sensor may be an NCAPS or MT-NCAPS. A linear position sensor may be used instead of an angular position sensor to generate the PWM signal.
1. A digital incremental encoder for generating output signals indicative of an angular position, a direction of rotation, and a speed of rotation of a shaft, comprising:
a counter for receiving a PWM signal indicative of the angular position of the shaft and a clock signal from an angular position sensor, and for generating a multi-bit output; and
a latch for latching the multi-bit output,
wherein the output signals are generated using a first bit and a second bit of the latched multi-bit output, the output signals comprising the first bit,
wherein the first bit and an XOR output generated from the first bit and the second bit have a quadrature phase relationship, the output signals further comprising the XOR output, and
wherein the direction of rotation of the shaft can be derived from the quadrature phase relationship between the first bit and the XOR output.
2. The digital incremental encoder of claim 1 , further comprising an XOR gate for receiving the first bit and the second bit of the latched multi-bit output, and for outputting the XOR output.
3. The digital incremental encoder of claim 1 , further comprising an AND gate for receiving and AND'ing a plurality of bits of the latched multi-bit output to generate an index signal indicative of a 360 degree rotation of the shaft,
wherein the plurality of bits can represent 100% duty cycle of the PWK signal.
4. The digital incremental encoder of claim 1 , wherein the counter starts counting the number of cycles of the clock in response to each first transitional edge of the PWM signal from a first state to a second state, and continues to count the number of cycles while the PWM signal remains at the second state.
5. The digital incremental encoder of claim 4 , wherein the counter is reset in response to each second transitional edge of the PWM signal from the second state to the first state.
6. The digital incremental encoder of claim 4 , wherein the multi-bit output is latched by the latch in response to each second transitional edge of the PWM signal from the second state to the first state.
7. A digital incremental encoder system for generating output signals indicative of an angular position, a direction of rotation, and a speed of rotation of a shaft, comprising:
an angular position sensor for generating a PWM signal indicative of the angular position of the shaft and a clock signal;
a counter for receiving the PWM signal and the clock signal, and generating a multi-bit output; and
a latch for latching the multi-bit output,
wherein the output signals are generated using a first bit and a second bit of the latched multi-bit output, the output signals comprising the first bit,
wherein the first bit and an XOR output generated from the first bit and the second bit have a quadrature phase relationship, the output signals further comprising the XOR output, and
wherein the direction of rotation of the shaft can be derived from the quadrature phase relationship between the first bit and the XOR output.
8. The digital incremental encoder system of claim 7 , further comprising an XOR gate for receiving the first bit and the second bit of the latched multi-bit output, and for outputting the XOR output.
9. The digital incremental encoder system of claim 7 , further comprising an AND gate for receiving and AND'ing a plurality of bits of the latched multi-bit output to generate an index signal indicative of a 360 degree rotation of the shaft,
wherein the plurality of bits can represent 100% duty cycle of the PWM signal.
10. The digital incremental encoder system of claim 7 , wherein the counter starts counting the number of cycles of the clock in response to each first transitional edge of the PWM signal from a first state to a second state, and continues to count the number of cycles while the PWM signal remains at the second state.
11. The digital incremental encoder system of claim 10 , wherein the counter is reset in response to each second transitional edge of the PWM signal from the second state to the first state.
12. The digital incremental encoder system of claim 10 , wherein the multi-bit output is latched by the latch in response to each second transitional edge of the PWM signal from the second state to the first state.
13. The digital incremental encoder system of claim 7 , wherein the angular position sensor is a non-contact angular position sensor (NCAPS) or a multi-turn non-contact angular position sensor (MT-NCAPS).
14. A method of generating output signals indicative of an angular position, a direction of rotation, and a speed of rotation of a shaft, comprising:
receiving a PWM signal indicative of the angular position of the shaft;
receiving a clock signal;
start counting a number of cycles of the clock signal in response to a first transitional edge of the PWM signal from a first state to a second state;
continue counting the number of cycles while the PWM signal remains at the second state to generate a multi-bit output representing the number of cycles counted;
latching the multi-bit output;
generating the output signals using a first bit and a second bit of the latched multi-bit output, the output signals comprising the first bit;
XOR'ing the first bit and the second bit of the latched multi-bit output to generate an XOR output, the output signals further comprising the XOR output, wherein the first bit and the XOR output have a quadrature phase relationship; and
deriving the direction of rotation of the shaft from the quadrature phase relationship.
15. The method of claim 14 , further comprising resetting the counter in response to a second transitional edge of the PWM signal from the second state to the first state.
16. The method of claim 15 , wherein said latching comprises latching responsive to the second transitional edge of the PWM signal.
17. The method of claim 14 , further comprising generating the PWM signal using an angular position sensor.
18. The method of claim 17 , wherein the angular position sensor is a non-contact angular position sensor (NCAPS) or a multi-turn NCAPS (MT-NCAPS).
19. The method of claim 14 , further comprising AND'ing a plurality of bits of the latched multi-bit output to generate an index signal, wherein the plurality of bits can represent 100% duty cycle of the PWM signal.
20. A digital incremental encoder for generating output signals indicative of a linear position, a direction of linear translation, and a speed of linear translation of the linear position being monitored by a linear position sensor, comprising:
a counter for receiving a PWM signal indicative of the linear position and a clock signal from the linear position sensor, and for generating a multi-bit output; and
a latch for latching the multi-bit output,
wherein the output signals are generated using a first bit and a second bit of the latched multi-bit output, the output signals comprising the first bit,
wherein the first bit and an xOR output generated from the first bit and the second bit have a quadrature phase relationship, the output signals further comprising the XOR output, and
wherein the direction of linear translation can be derived from the quadrature phase relationship between the first bit and the XOR output.
21. The digital incremental encoder of claim 20 , further comprising an XOR gate for receiving the first bit and the second bit of the latched multi-bit output, and for outputting the XOR output.