Methods of fabricating contact regions for FET incorporating SiGe
View Patent ↗Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
1. A method comprising:
providing a gate stack disposed above a first area of a substrate, the gate stack comprising a gate oxide disposed beneath a conductive gate material, the substrate comprising a strained layer over a first relaxed layer;
epitaxially depositing a SiGe layer in at least one area of said substrate adjacent to the first area of said substrate;
providing a metal layer over said SiGe layer, said metal layer comprising Ni; and
reacting said metal layer with said SiGe layer to form a region comprising at least one of silicide or silicide/germanicide disposed over and in direct contact with unreacted SiGe,
wherein the region comprising at least one of silicide or silicide/germanicide forms a contact region for a source or a drain of a FET, and wherein a channel region of the FET comprises a portion of the strained layer.
2. The method of claim 1 , wherein said SiGe layer is substantially strained.
3. The method of claim 1 , wherein said gate stack defines the channel region disposed thereunder.
4. The method of claim 1 , wherein the step of reacting said metal layer with said SiGe layer comprises thermal annealing.
5. The method of claim 1 , wherein the strain in the strained layer is induced by lattice mismatch to the first relaxed layer.
6. The method of claim 1 , wherein said substrate has a first Ge concentration and said SiGe layer has a second Ge concentration exceeding the first Ge concentration.
7. The method of claim 1 , further comprising forming a shallow trench isolation region such that said region comprising at least one of silicide and silicide/germanicide is disposed proximate to said shallow trench isolation region.
8. The method of claim 1 , further comprising implanting dopants into said at least one area of the substrate prior to epitaxially depositing said SiGe layer.
9. The method of claim 1 , further comprising forming a spacer proximate said gate stack prior to providing said metal layer.
10. The method of claim 1 , wherein said substrate comprises an insulator layer, the first relaxed layer being over and adjoining the insulator layer.
11. The method of claim 10 , wherein said substrate comprises Si.
12. The method of claim 2 , wherein said SiGe layer is compressively strained.
13. The method of claim 1 , wherein said strained layer comprises Si.
14. The method of claim 1 , wherein the strained layer consists essentially of Si.
15. The method of claim 14 , wherein said SiGe layer is substantially strained.
16. A method comprising:
providing a gate stack disposed above a first area of a substrate, the gate stack comprising a gate oxide disposed beneath a conductive gate material, the substrate comprising a strained layer over a relaxed layer;
epitaxially depositing a first semiconductor layer in at least one area of the substrate adjacent to the first area of the substrate;
providing a metal layer over the semiconductor layer, the metal layer comprising Ni; and
reacting the metal layer with the semiconductor layer to form a reacted region comprising a semiconductor material reacted with a metal, the reacted region being disposed over and in direct contact with an unreacted portion of the relaxed layer,
wherein the reacted region forms a contact region for a source or a drain of a FET, and wherein a channel region of the FET comprises a portion of the strained layer.
17. The method of claim 16 , wherein the substrate comprises an insulator layer, the relaxed layer being over and adjoining the insulator layer.
18. The method of claim 16 , wherein the substrate comprises a second semiconductor layer over the strained layer, the second semiconductor layer having a different composition than the strained layer.