IP Library Granted Patent US 7,157,287
Granted Patent B2
US 7,157,287 · App. 10/855,088 · Granted Jan 2, 2007

Method of substrate surface treatment for RRAM thin film deposition

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Quick Facts
Patent No.
US 7,157,287
App. No.
10/855,088
Granted
Jan 2, 2007
Kind
B2
Abstract

A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.

Claims (54)

1. A method of fabricating a CMR thin film for use in a semiconductor device, comprising:

preparing a CMR precursor in the form of a metal acetate based acetic acid solution;

preparing a wafer;

placing a wafer in a spin-coating chamber;

spin-coating and heating the wafer according to the following:

injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber;

accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds;

baking the wafer at a temperature of about 180° C. for about one minute;

ramping the temperature to about 230° C.;

baking the wafer for about one minute at the ramped temperature;

annealing the wafer at about 500° C. for about five minutes;

repeating said spin-coating and heating steps at least three times;

post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and

completing the semiconductor device.

2. The method of claim 1 wherein said preparing a wafer includes forming a layer of rhodium having a surface treatment of Pt 0.2 Co 0.8 alloy thereon.

3. The method of claim 1 wherein said preparing includes forming a layer of Rh—Pt—Co alloy thereon.

4. The method of claim 1 wherein said preparing includes forming a layer of SiO 2 on a silicon wafer.

5. The method of claim 1 which includes programming the device by applying a writing pulse having an amplitude of at least 4.5V and a pulse width of at least 50 ns.

6. The method of claim 1 which includes programming the device by applying a reset pulse having a minimum pulse amplitude at least 2V and a pulse width of at least 2 μs.

7. A method of fabricating a CMR thin film for use in a semiconductor device, comprising:

preparing a CMR precursor in the form of a metal acetate based acetic acid solution;

preparing a wafer, including forming a layer of material on a silicon substrate, wherein the material is taken from the group of materials consisting of a layer of rhodium having a surface treatment of Pt 0.2 Co 0.8 alloy thereon and a layer of Rh—Pt—Co alloy thereon;

placing a wafer in a spin-coating chamber;

spin-coating and heating the wafer according to the following:

injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber;

accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds;

baking the wafer at a temperature of about 180° C. for about one minute;

ramping the temperature to about 230° C.;

baking the wafer for about one minute at the ramped temperature;

annealing the wafer at about 500° C. for about five minutes;

repeating said spin-coating and heating steps at least three times;

post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and

completing the semiconductor device.

8. The method of claim 7 wherein said preparing includes forming a layer of SiO 2 on a silicon wafer.

9. The method of claim 7 which includes programming the device by applying a writing pulse having an amplitude of at least 4.5V and a pulse width of at least 50 ns.

10. The method of claim 7 which includes programming the device by applying a reset pulse having a minimum pulse amplitude at least 2V and a pulse width of at least 2 μs.

11. A method of fabricating a CMR thin film for use in a semiconductor device, comprising:

preparing a CMR precursor in the form of a metal acetate based acetic acid solution;

preparing a wafer;

placing a wafer in a spin-coating chamber;

spin-coating and heating the wafer according to the following:

injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber;

accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds;

baking the wafer at a temperature of about 180° C. for about one minute;

ramping the temperature to about 230° C.;

baking the wafer for about one minute at the ramped temperature;

annealing the wafer at about 500° C. for about five minutes;

repeating said spin-coating and heating steps at least three times;

post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air;

completing the semiconductor device; and

programming the device by applying a writing pulse having an amplitude of at least 4.5V and a pulse width of at least 50 ns and by applying a reset pulse having a minimum pulse amplitude at least 2V and a pulse width of at least 2 μs.

12. The method of claim 11 wherein said preparing a wafer includes forming a layer of rhodium having a surface treatment of Pt 0.2 Co 0.8 alloy thereon.

13. The method of claim 11 wherein said preparing includes forming a layer of Rh—Pt—Co alloy thereon.

14. The method of claim 11 wherein said preparing includes forming a layer of SiO 2 on a silicon wafer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2013
From: INTELLECTUAL PROPERTIES I KFT.
To: XENOGENIC DEVELOPMENT LIMITED LIABILITY COMPANY
Reel/Frame 029632/0534 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2013
From: SHARP KABUSHIKI KAISHA
To: INTELLECTUAL PROPERTIES I KFT.
Reel/Frame 029574/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2007
From: SHARP LABORATORIES OF AMERICA, INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 019795/0623 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2004
From: ZHUANG, WEI-WEI; LI, TINGKAI; PAN, WEI; EVANS, DAVID R.; HSU, SHENG TENG
To: SHARP LABORATORIES OF AMERICA, INC.
Reel/Frame 015404/0208 →