Method and apparatus for generating circuit model for static noise analysis

1. A method for generating a circuit model for analyzing noise in an electronic circuit, the electronic circuit including a victim circuit and aggressor circuits affecting the victim circuit, said method comprising:

analyzing the electronic circuit to determine a first circuit parameter for each of the victim circuit and the aggressor circuits and a second circuit parameter for each of the aggressor circuits;

ordering the aggressor circuits based on the first and second circuit parameters thereof;

setting a current model parameter of the circuit model to an initial value;

selecting a first aggressor circuit in accordance with said ordering;

determining whether to reduce the selected aggressor circuit into a virtual attacker model before inserting into the circuit model based on the first circuit parameter thereof;

updating the current model parameter in accordance with either the selected aggressor circuit or the virtual attacker model thereof to be inserted;

inserting either the selected aggressor circuit or the virtual attacker model thereof to the circuit model in accordance with said determining;

selecting a next aggressor circuit based on said ordering; and

iteratively repeating said determining, said updating, said inserting, and said selecting a next aggressor circuit;

wherein said ordering comprises:

calculating an ordering factor for each aggressor circuit, the ordering factor being a function of the first circuit parameter and the second circuit parameter, further wherein the first circuit parameter represents a size of the circuit and the second circuit parameter represents a noise strength of the circuit, the ordering factor of each aggressor circuit being expressed as:

F ( S,N )= S/S MAX +( N MAX −N )/ N MAX ,

where S is the size of the aggressor circuit, N is the noise strength of the aggressor circuit, S MAX is the size of the largest aggressor circuit, and N MAX is the noise strength of the strongest aggressor circuit.

2. An apparatus for generating a circuit model for analyzing noise in an electronic circuit, said apparatus comprising:

an analyzer adapted to receive an RC netlist of the electronic circuit, the electronic circuit including a victim circuit and aggressor circuits affecting the victim circuit, said analyzer being adapted to analyze the electronic circuit to determine a first circuit parameter for each of the victim circuit and the aggressor circuits and a second circuit parameter for each of the aggressor circuits;

an ordering module coupled to said analyzer, adapted to order the aggressor circuits based on the first and second circuit parameters thereof;

a circuit selector coupled to said ordering module, adapted to iteratively select an aggressor circuit in accordance with the sorted order;

a modeling module coupled to said circuit selector, adapted to determine whether the selected aggressor circuit is to be reduced into a virtual attacker model based on the first parameter of the selected aggressor circuit and a current model parameter for the circuit model;

a model parameter module coupled to said modeling module, adapted to update the current model parameter based on the selected aggressor circuit or the virtual attacker model thereof to be inserted to the circuit model; and

a circuit inserter coupled to said modeling module, adapted to insert either the selected aggressor circuit or the virtual attacker model thereof to the circuit model based on the determination by said modeling module, wherein;

said ordering module comprises:

a factor calculator adapted to calculate an ordering factor for each aggressor circuit, the ordering factor being a function of the first and second circuit parameters, further wherein the first circuit parameter represents a size of the circuit and the second circuit parameter represents a noise strength of the circuit, the ordering factor of each aggressor circuit being expressed as:

F ( S,N )= S/S MAX +( N MAX −N )/ N MAX ,

where S is the size of the aggressor circuit, N is the noise strength of the aggressor circuit, S MAX is the size of the largest aggressor circuit, and N MAX is the noise strength of the strongest aggressor circuit.

3. A method for generating a circuit model for analyzing noise in an electronic circuit, the electronic circuit including a victim circuit and aggressor circuits affecting the victim circuit, said method comprising:

analyzing the electronic circuit to determine a size of each of the victim circuit and the aggressor circuits and a noise strength of each of the aggressor circuits, the noise strength reflecting an estimated amount of noise injected onto the victim circuit;

assigning an ordering factor to each of the aggressor circuits, the ordering factor being a function of the size and the noise strength of the aggressor circuit, a larger size increasing the ordering factor and a greater noise strength decreasing the ordering factor;

ordering the aggressor circuits in an order of increasing ordering factors;

setting a current model size of the circuit model to a size of the victim circuit;

selecting a first aggressor circuit in accordance with the order;

determining if a sum of the current model size and the size of the selected aggressor circuit exceeds a predetermined size;

incrementing the current model size by the size of the selected aggressor circuit if the sum does not exceed the predetermined size, and inserting the selected aggressor circuit into the circuit model;

incrementing the current model size by a unit size if the sum exceeds the predetermined size, and inserting a virtual attacker model of the selected aggressor circuit into the circuit model;

selecting a next aggressor circuit based on said ordering; and

iteratively repeating said determining, said incrementing and inserting, and said selecting a next aggressor circuit.

4. An apparatus for generating a circuit model for analyzing noise in an electronic circuit, the electronic circuit including a victim circuit and aggressor circuits affecting the victim circuit, said apparatus comprising:

means for analyzing the electronic circuit to determine a first circuit parameter for each of the victim circuit and the aggressor circuits and a second circuit parameter for each of the aggressor circuits;

means for ordering the aggressor circuits based on the first and second circuit parameters thereof;

means for setting a current model parameter of the circuit model to an initial value;

means for selecting a first aggressor circuit in accordance with said ordering;

means for determining whether to reduce the selected aggressor circuit into a virtual attacker model before inserting into the circuit model based on the first circuit parameter thereof;

means for updating the current model parameter in accordance with either the selected aggressor circuit or the virtual attacker model thereof to be inserted;

means for inserting either the selected aggressor circuit or the virtual attacker model thereof to the circuit model in accordance with said determining;

means for selecting a next aggressor circuit based on said ordering; and

means for iteratively repeating said determining, said updating, said inserting, and said selecting a next aggressor circuit, wherein;

said means for ordering comprises:

means for calculating an ordering factor for each aggressor circuit, the ordering factor being a function of the first circuit parameter and the second circuit parameter, further wherein the first circuit parameter represents a size of the circuit and the second circuit parameter represents a noise strength of the circuit, the ordering factor of each aggressor circuit being expressed as:

F ( S,N )= S/S MAX +( N MAX −N )/ N MAX ,

where S is the size of the aggressor circuit, N is the noise strength of the aggressor circuit, S MAX is the size of the largest aggressor circuit, and N MAX is the noise strength of the strongest aggressor circuit.

5. An apparatus for generating a circuit model for analyzing noise in an electronic circuit, the electronic circuit including a victim circuit and aggressor circuits affecting the victim circuit, said apparatus comprising:

means for analyzing the electronic circuit to determine a size of each of the victim circuit and the aggressor circuits and a noise strength of each of the aggressor circuits, the noise strength reflecting an estimated amount of noise injected onto the victim circuit;

means for assigning an ordering factor to each of the aggressor circuits, the ordering factor being a function of the size and the noise strength of the aggressor circuit, a larger size increasing the ordering factor and a greater noise strength decreasing the ordering factor;

means for ordering the aggressor circuits in an order of increasing ordering factors;

means for setting a current model size of the circuit model to a size of the victim circuit;

means for selecting a first aggressor circuit in accordance with the order;

means for determining if a sum of the current model size and the size of the selected aggressor circuit exceeds a predetermined size;

means for incrementing the current model size by the size of the selected aggressor circuit if the sum does not exceed the predetermined size, and inserting the selected aggressor circuit into the circuit model;

means for incrementing the current model size by a unit size if the sum exceeds the predetermined size, and inserting a virtual attacker model of the selected aggressor circuit into the circuit model;

means for selecting a next aggressor circuit based on said ordering; and

means for iteratively repeating said determining, said incrementing and inserting, and said selecting a next aggressor circuit.

6. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for generating a circuit model for analyzing noise in an electronic circuit, the electronic circuit including a victim circuit and aggressor circuits affecting the victim circuit, said method comprising:

analyzing the electronic circuit to determine a first circuit parameter for each of the victim circuit and the aggressor circuits and a second circuit parameter for each of the aggressor circuits;

ordering the aggressor circuits based on the first and second circuit parameters thereof;

setting a current model parameter of the circuit model to an initial value;

selecting a first aggressor circuit in accordance with said ordering;

determining whether to reduce the selected aggressor circuit into a virtual attacker model before inserting into the circuit model based on the first circuit parameter thereof;

updating the current model parameter in accordance with either the selected aggressor circuit or the virtual attacker model thereof to be inserted;

inserting either the selected aggressor circuit or the virtual attacker model thereof to the circuit model in accordance with said determining;

selecting a next aggressor circuit based on said ordering; and

iteratively repeating said determining, said updating, said inserting, and said selecting a next aggressor circuit, wherein;

said ordering comprises:

calculating an ordering factor for each aggressor circuit, the ordering factor being a function of the first circuit parameter and the second circuit parameter, further wherein the first circuit parameter represents a size of the circuit and the second circuit parameter represents a noise strength of the circuit, the ordering factor of each aggressor circuit being expressed as:

F ( S,N )= S/S MAX +( N MAX −N )/ N MAX ,

where S is the size of the aggressor circuit, N is the noise strength of the aggressor circuit, S MAX is the size of the largest aggressor circuit, and N MAX is the noise strength of the strongest aggressor circuit.

7. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for generating a circuit model for analyzing noise in an electronic circuit, the electronic circuit including a victim circuit and aggressor circuits affecting the victim circuit, said method comprising:

analyzing the electronic circuit to determine a size of each of the victim circuit and the aggressor circuits and a noise strength of each of the aggressor circuits, the noise strength reflecting an estimated amount of noise injected onto the victim circuit;

assigning an ordering factor to each of the aggressor circuits, the ordering factor being a function of the size and the noise strength of the aggressor circuit, a larger size increasing the ordering factor and a greater noise strength decreasing the ordering factor;

ordering the aggressor circuits in an order of increasing ordering factors;

setting a current model size of the circuit model to a size of the victim circuit;

selecting a first aggressor circuit in accordance with the order;

determining if a sum of the current model size and the size of the selected aggressor circuit exceeds a predetermined size;

incrementing the current model size by the size of the selected aggressor circuit if the sum does not exceed the predetermined size, and inserting the selected aggressor circuit into the circuit model;

incrementing the current model size by a unit size if the sum exceeds the predetermined size, and inserting a virtual attacker model of the selected aggressor circuit into the circuit model;

selecting a next aggressor circuit based on said ordering; and

iteratively repeating said determining, said incrementing and inserting, and said selecting a next aggressor circuit.