IP Library Granted Patent US 7,324,561
Granted Patent B1
US 7,324,561 · App. 10/857,054 · Granted Jan 29, 2008

Systems and methods for generating an output oscillation signal with low jitter

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Quick Facts
Patent No.
US 7,324,561
App. No.
10/857,054
Granted
Jan 29, 2008
Kind
B1
Abstract

A circuit for generating an output oscillation signal with low jitter includes an oscillator to generate an oscillation signal at an initial frequency based upon a control input to vary an amplitude of the oscillation signal. A first frequency multiplier multiplies the oscillation signal to result in a first signal with first frequency and first undesired frequency components. A filter minimizes the first undesired frequency components of the first signal. A second frequency multiplier multiplies the first signal to result in the output oscillation signal with second frequency and second undesired frequency components. A second feedback circuit compares a predetermined range and at least one of the first signal and the output oscillation signal to result in a reference value. A first feedback circuit varies the control input based upon a comparison between the reference value and the amplitude of the oscillation signal to minimize the second undesired frequency components.

Claims (50)

1. A circuit for generating an output oscillation signal with low jitter, the circuit comprising:

an oscillator configured to generate an initial oscillation signal at an initial frequency, the oscillator having a control input to vary an amplitude of the initial oscillation signal;

a first frequency multiplier configured to multiply the initial frequency of the initial oscillation signal to result in a first signal with first frequency and first undesired frequency components;

a filter configured to minimize the first undesired frequency components of the first signal;

a second frequency multiplier configured to multiply the first signal to result in the output oscillation signal with second frequency and second undesired frequency components;

a second feedback circuit configured to compare a predetermined range and at least one of the first signal and the output oscillation signal to result in a reference value; and

a first feedback circuit configured to vary the control input based upon a comparison between the reference value and the amplitude of the initial oscillation signal to minimize the second undesired frequency components.

2. The circuit of claim 1 , wherein the oscillator comprises a quartz crystal.

3. The circuit of claim 1 , wherein the oscillator comprises a surface-acoustic wave resonator.

4. The circuit of claim 1 , wherein the oscillator comprises a ceramic resonator.

5. The circuit of claim 1 , wherein the oscillator comprises an inductor-capacitor resonator.

6. The circuit of claim 1 , wherein the predetermined range comprises a high amplitude threshold and a low amplitude threshold.

7. The circuit of claim 1 , wherein the first feedback circuit comprises:

a peak detector configured to convert the amplitude of the initial oscillation signal to an input signal; and

a subtractor configured to vary the control input by converting the reference value into a reference signal and comparing the input signal and the reference signal.

8. The circuit of claim 1 , wherein the first feedback circuit comprises:

a peak detector configured to convert the amplitude of the initial oscillation signal to an input current; and

a subtractor configured to vary the control input by converting the reference value into a reference current and subtracting the input current from the reference current.

9. The circuit of claim 1 , wherein the reference value comprises a digital word.

10. The circuit of claim 1 , further comprising at least one amplifier to vary the amplitude of the oscillation signal based upon the control input.

11. The circuit of claim 10 , wherein the at least one amplifier comprises at least one transconductance amplifier.

12. The circuit of claim 1 , further comprising a comparator configured to convert the output oscillation signal to a digital waveform.

13. The circuit of claim 12 , further comprising an output circuit configured to convert the digital waveform to multiple digital signal formats.

14. The circuit of claim 1 , further comprising a tuning circuit configured to tune the filter based upon the initial frequency.

15. The circuit of claim 1 , further comprising a buffer configured to amplify the initial oscillation signal.

16. The circuit of claim 1 , further comprising a tuning circuit configured to tune the initial frequency of the initial oscillation signal.

17. The circuit of claim 16 , wherein the tuning circuit comprises at least one varactor.

18. A method for generating an output oscillation signal with low jitter, the method comprising:

generating an initial oscillation signal at an initial frequency based upon a control input to vary an amplitude of the initial oscillation signal;

multiplying the initial frequency of the initial oscillation signal to result in a first signal with first frequency and first undesired frequency components;

filtering the first signal to minimize the first undesired frequency components;

multiplying the first signal to result in the output oscillation signal with second frequency and second undesired frequency components;

comparing a predetermined range and an amplitude of at least one of the first signal and the output oscillation signal to result in a reference value; and

varying the control input based upon a comparison between the reference value and the amplitude of the initial oscillation signal to minimize the second undesired frequency components.

19. The method of claim 18 , wherein varying the control input comprises:

converting the amplitude of the initial oscillation signal into an input signal;

converting the reference value into a reference signal; and

comparing the input signal and the reference signal.

20. The method of claim 18 , wherein at least one amplifier receives the control input to vary the amplitude of the oscillation signal.

21. The method of claim 20 , wherein the at least one amplifier comprises at least one transconductance amplifier.

22. The method of claim 18 , wherein varying the control input comprises:

converting the amplitude of the initial oscillation signal into an input current;

converting the reference value into a reference current; and

subtracting the input current from the reference current.

23. The method of claim 18 , further comprising amplifying the initial oscillation signal.

24. The method of claim 18 , wherein filtering to minimize the first undesired frequency components is based upon the initial frequency.

25. The method of claim 18 , further comprising converting the output oscillation signal to a digital waveform.

26. The method of claim 25 , further comprising converting the digital waveform to multiple digital signal formats.

27. The method of claim 18 , wherein the predetermined range comprises a high amplitude threshold and a low amplitude threshold.

28. The method of claim 18 , wherein the reference value comprises a digital word.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2010
From: SILICON LABS SC, INC.
To: SILICON LABORATORIES INC.
Reel/Frame 025366/0466 →
CHANGE OF NAME Recorded May 4, 2010
From: SILICON CLOCKS, INC.
To: SILICON LABS SC, INC.
Reel/Frame 024369/0134 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2006
From: SISINC SEMICONDUCTOR, INC.
To: SILICON CLOCKS INC.
Reel/Frame 018106/0528 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2004
From: MILLER, RICHARD; DUMITRESCU, GABRIEL-GHEORGHE; OPRIS, ION E.
To: SISINC SEMICONDUCTOR, INC.
Reel/Frame 015412/0816 →